Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.

Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.

Abstract: The method of the present disclosure permits the synthesis of any virtual cell by means of an abstraction, including that of an enable flop, full adder, half adder, or multi-stage multiplexer, based on the ability to extract timing information and add a timing margin to account for clock latency. Specifically, the method of the present disclosure takes advantage of the ability to create synthesis abstractions to build a model of a clock gated enable flop. The synthesis abstraction operates on the assumption that every enable flop has an internally gated clock. The synthesis abstraction may be constructed according to various scripts or algorithms.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a voltage source. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to the voltage source or a different voltage source. When a clock signal is in a first state, the first single transistor is activated to reset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to reset the digital storage element.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: The system and method disclosed here are directed to desensitization of paths to perturbations resulting from manufacturing faults. A threshold value for signal slew filters out some near-critical paths, and a mathematical formula is applied to determine the appropriate upsize for the cell driving the net along the near-critical path. The cell driving the net may be then be upsized in order to improve the timing through the cell, increase the positive slack, and reduce the sensitivity of the net to design perturbations.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical ground. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to electrical ground. When a clock signal is in a first state, the first single transistor is activated to preset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to preset the digital storage element.

Abstract: A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay.

Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.