Abstract: A transistor substrate for a liquid crystal display comprises an array of insulated-gate staggered TFTs and a capacitor (36) associated with each transistor. The gate insulator (400,420) comprises a first inorganic layer (400) and a second, polymer or spin-on glass layer (420), of which layers only the polymer or spin-on glass layer (420) extends to the capacitor (36) to define the capacitor dielectric.

Abstract: A method of forming an active plate for a liquid crystal display using top gate TFTs is described. A black organic light shield layer (73) is used under the TFTs to shield the channel (91) of the TFTs from light passing through a substrate (71) from below. The active plate may be a high aperture plate having pixel electrodes (99) overlapping the row and column (79) conductors. The organic light shield layer may mask the gaps (102) between pixel electrodes.

Abstract: A matrix display device (100) comprises an array of pixels (25) for producing a display output in response to voltages applied by drive circuit means (10,16,68). Each pixel (25) has a cell (18) comprising electro-optical material between two electrodes (5,6), the polarity of the voltage applied across the electrodes of each cell being periodically inverted. The device includes correction means (72) for modifying voltages generated by the drive circuit means (10,16,68) to compensate for display artefacts, such as flicker. The correction means comprises a measurement pixel (25a) and means for generating for each of the voltage polarities applied across the electrodes (18a) of the cells (18) a respective signal indicative of the capacitance of the measurement pixel cell, the correction means (72) modifying voltages generated by the drive circuit means (10,16,68) in response to said signals.

Abstract: A method of forming an active plate for a liquid crystal display includes depositing and patterning a gate conductor layer over an insulating substrate; depositing a gate insulator layer over the patterned gate conductor layer; depositing a silicon layer over the gate insulator layer; depositing arid patterning a source and drain conductor layer over the silicon layer; and forming a pixel electrode layer for contacting one of the source and drain of the transistor. The silicon layer includes plasma deposition from a gas comprising at least a compound including an n-type dopant atom and a gas containing silicon, with the ratio of the volume of the compound to the volume of the gas containing silicon being selected to give a doping density of the n-type dopant atoms in the silicon layer of between 2.5×1016 and 1.5×1018 atoms per cm3.

Abstract: A method of forming an active plate for a liquid crystal display is disclosed in which the source and drain conductors (28, 30), pixel electrodes (38) and column conductors (32) are formed by depositing and patterning a transparent conductor layer. There is selective plating of areas (52; 60) of the transparent conductor layer to form a metallic layer for reducing the resistivity of the transparent conductor layer. The plated areas include the column conductors (32) but exclude the source and drain conductors and the pixel electrodes. This enables the column conductors to be treated to reduce the resistivity, but without altering the channel length of the transistor because the source and drain parts of the layer are shielded from the plating process.

Abstract: The storage capacitor of an active matrix liquid crystal display is formed to have a second electrode 28 with a plurality of fingers 50 extending over the first electrode 10. The drain electrode 30 and the second electrode 28 of the storage capacitor may be formed from a single metallization layer. The width of the drain electrode 30 and the fingers 50 of the second electrode 10 will tend to vary in parallel as a result of any process variation in the manufacturing process. The feature that the widths vary in parallel tends to cancel out variation in the kick back voltage.

Abstract: An active matrix device comprises a supporting plate (20), an array of control elements (6), a set of row address conductors (26) on the plate for addressing the array to which selection signals are applied by a row driver circuit (22), and a set of column address conductors (12) on the plate to which data signals are applied by a column driver circuit (22) for conduction to the array. Connection from the respective driver circuits (22) to at least some of both sets of address conductors is via the same side of the array, the profile of the plate around the other sides of the array being non-rectangular. Greater flexibility in the design of such devices is thus provided.

Abstract: The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).

Abstract: The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).

Abstract: An electronic device (10) comprises an array of pixels (12), arranged in rows and columns (14,16) with row and column address lines (18,20) for addressing each pixel (12). Each row and column address line is connected to two discharge lines (30,32) through a discharge circuit (38). The circuit allows the passage of charge between the address line and the first discharge line (30) when the address line is at a potential below that of the first discharge line, and allows the passage of charge between the address line and the second discharge line (32) when the address line is at a potential above that of the second discharge line. This provides electrostatic discharge protection against an increase or decrease in voltage on the row or column address lines during manufacture of the device. By providing suitable voltages on the two discharge lines during operation of the manufactured device, it is possible to prevent the discharge circuit from operating, thereby saving power.

Abstract: A method of manufacturing thin film transistors includes the steps of depositing and patterning a plurality of layers (3,13,15,23) to define the thin film transistors, wherein one of the plurality of layers (23) is patterned using a higher definition process and others (3,13,15) of the plurality of layers are patterned using a lower definition process. In particular, a metallisation layer (23) defining the source and drain of the thin film transistors may be patterned using the high definition process and the other layers patterned by the low definition process. The high definition process may be photolithography and the low definition process may be printing.

Abstract: A light-weight substrate (10) for thin film, large area electronic devices such as active matrix display devices, image sensing arrays and the like comprises a layer of rigid, cellular material (12) bonded to a comparatively thin glass sheet (11) on whose surface thin film circuit elements are provided. An aerogel material of higher than usual density can be used for the cellular layer. An array of microlenses may be provided between the cellular layer and the thin glass sheet.

Abstract: A method of manufacturing thin film transistors includes the steps of depositing and patterning a plurality of layers (3,13,15,23) to define the thin film transistors, wherein one of the plurality of layers (23) is patterned using a higher definition process and others (3,13,15) of the plurality of layers are patterned using a lower definition process. In particular, a metallization layer (23) defining the source and drain of the thin film transistors may be patterned using the high definition process and the other layers patterned by the low definition process. The high definition process may be photolithography and the low definition process may be printing.

Abstract: An insulated-gate thin film transistor comprises a gate electrode and source (20) and drain (24) electrodes. The source and drain electrodes are laterally spaced apart, and are vertically separated from the gate electrode (12) by a gate insulator layer and an amorphous silicon layer. A region of the amorphous silicon layer (16) is vertically aligned with the lateral spacing between the source and drain electrodes defining the transistor channel, and the region of the amorphous silicon layer has a thickness of less than 100 nm, and is doped with phosphorus atoms with a doping density of between 2.5×1016 and 1.5×1018 atoms per cm3.

Abstract: Short channel thin film transistors suffer from unacceptably high leakage currents. The invention provides an electronic device including a thin film transistor in which the length (20) of the channel of the transistor is 1 &mgr;m or less, and the mobility of the semiconductor material in the channel is less than 0.2 cm2/Vs. The selection of a low mobility semiconductor material results in acceptable off-current characteristics and its effect on the switching speed of the device is compensated for by the short channel length (20) of the device.

Abstract: An insulated-gate thin film transistor comprises a gate electrode and source and drain electrodes. The source and drain electrodes are laterally spaced apart, and are vertically separated from the gate electrode by a gate insulator layer and an amorphous silicon layer. A region of the amorphous silicon layer is vertically aligned with the lateral spacing between the source and drain electrodes defining the transistor channel, and the region of the amorphous silicon layer has a thickness of less than 100 nm, and is doped with phosphorus atoms with a doping density of between 2.5×1016 and 1.5×1018 atoms per cm3. This enables the mobility to be increased so that the thickness reduction of the silicon layer can be tolerated. This thickness reduction enables the photosensitivity of the layer to be reduced sufficiently to avoid the need for a black mask layer.

Abstract: A matrix display device (100) comprises an array of pixels (25) for producing a display output in response to voltages applied by drive circuit means (10,16,68). Each pixel (25) has a cell (18) comprising electro-optical material between two electrodes (5,6), the polarity of the voltage applied across the electrodes of each cell being periodically inverted. The device includes correction means (72) for modifying voltages generated by the drive circuit means (10,16,68) to compensate for display artefacts, such as flicker. The correction means comprises a measurement pixel (25a) and means for generating for each of the voltage polarities applied across the electrodes (18a) of the cells (18) a respective signal indicative of the capacitance of the measurement pixel cell, the correction means (72) modifying voltages generated by the drive circuit means (10,16,68) in response to said signals.

Abstract: An electronic device (10) comprises an array of pixels (12), arranged in rows and columns (14,16) with row and column address lines (18,20) for addressing each pixel (12). Each row and column address line is connected to two discharge lines (30,32) through a discharge circuit (38). The circuit allows the, passage of charge between the address line and the first discharge line (30) when the address line is at a potential below that of the first discharge line, and allows the passage of charge between the address line and the second discharge line (32) when the address line is at a potential above that of the second discharge line. This provides electrostatic discharge protection against an increase or decrease in voltage on the row or column address lines during manufacture of the device. By providing suitable voltages on the two discharge lines during operation of the manufactured device, it is possible to prevent the discharge circuit from operating, thereby saving power.

Abstract: The storage capacitor of an active matrix liquid crystal display is formed to have a second electrode 28 with a plurality of fingers 50 extending over the first electrode 10. The drain electrode 30 and the second electrode 28 of the storage capacitor may be formed from a single metallization layer. The width of the drain electrode 30 and the fingers 50 of the second electrode 10 will tend to vary in parallel as a result of any process variation in the manufacturing process. The feature that the widths vary in parallel tends to cancel out variation in the kick back voltage.

Abstract: The storage capacitor of an active matrix liquid crystal display is formed to have a second electrode (28) that laterally overlaps a first electrode (10). The drain (30) of a thin film transistor extends across the gate electrode (2). The gate electrode (2) and the first electrode (10) of the storage capacitor are formed from a single metallization layer. The width of the gate electrode (2) and the first electrode (10) will tend to vary in parallel, as a result of process variation. This parallel variation tends to cancel out subsequent variation in the kick back voltage.