Patents by Inventor Steven C. H. Hung
Steven C. H. Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961734Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.Type: GrantFiled: April 26, 2022Date of Patent: April 16, 2024Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
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Patent number: 11955332Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.Type: GrantFiled: June 17, 2022Date of Patent: April 9, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
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Patent number: 11923441Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Patent number: 11888045Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitriride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).Type: GrantFiled: December 21, 2021Date of Patent: January 30, 2024Assignee: Applied Materials, Inc.Inventors: Yongjing Lin, Karla M Bernal Ramos, Luping Li, Shih Chung Chen, Jacqueline S. Wrench, Yixiong Yang, Steven C. H. Hung, Srinivas Gandikota, Naomi Yoshida, Lin Dong
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Publication number: 20230402291Abstract: A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.Type: ApplicationFiled: May 16, 2023Publication date: December 14, 2023Inventors: Steven C. H. HUNG, Yixiong YANG, Tianyi HUANG, Srinivas GANDIKOTA
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Publication number: 20230377901Abstract: A method of forming a structure on a substrate is provided. The method includes depositing a dipole dopant containing (DDC) layer including a dipole dopant on a first and second region of a dielectric layer (DL) of the substrate. A hardmask (HM) is deposited over the DDC deposited on the first and the second regions. A patterned photoresist layer (PR) is formed over the HM. The PR includes a first portion that is positioned over the first region and an opening that is positioned to expose a portion of the HM that is disposed over the second region of the substrate. The HM and DDC within the second region are etched and at least a portion of the DL is exposed within the second region. The PR is removed and the substrate is annealed to diffuse the dipole dopant into a portion of the DL disposed in the first region.Type: ApplicationFiled: April 26, 2023Publication date: November 23, 2023Applicant: Applied Materials, Inc.Inventors: Steven C. H. HUNG, Srinivas GANDIKOTA, Yixiong YANG, Yong YANG
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Publication number: 20230260791Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-? dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-? dielectric layer on the interfacial layer, and a metal film on the high-? dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-? dielectric layer.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Yixiong Yang, Steven C.H. Hung, Tianyi Huang, Seshadri Ganguli
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Publication number: 20230253466Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Applicant: Applied Materials, Inc.Inventors: Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C.H. Hung, Srinivas Gandikota
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Patent number: 11658218Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).Type: GrantFiled: February 10, 2022Date of Patent: May 23, 2023Assignee: Applied Materials, Inc.Inventors: Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C. H. Hung, Srinivas Gandikota
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Publication number: 20230097400Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 ? to less than or equal to 50 ?. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-? metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Steven C.H. Hung, Mandyam Sriram, Jacqueline S. Wrench, Yixiong Yang, Yong Yang
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Publication number: 20230010499Abstract: Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a thermal treatment chamber coupled with the first transfer chamber. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a metal deposition chamber coupled with the second transfer chamber.Type: ApplicationFiled: July 7, 2022Publication date: January 12, 2023Applicant: Applied Materials, Inc.Inventors: Brian K. Kirkpatrick, Steven C. H. Hung, Malcolm J. Bevan
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Patent number: 11552177Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 ? to less than or equal to 50 ?. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-? metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.Type: GrantFiled: September 4, 2020Date of Patent: January 10, 2023Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Steven C. H. Hung, Mandyam Sriram, Jacqueline S. Wrench, Yixiong Yang, Yong Yang
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Publication number: 20220399457Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: ApplicationFiled: August 16, 2022Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20220328308Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.Type: ApplicationFiled: June 17, 2022Publication date: October 13, 2022Inventors: Srinivas GANDIKOTA, Yixiong YANG, Jacqueline Samantha WRENCH, Yong YANG, Steven C. H. HUNG
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Patent number: 11456178Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.Type: GrantFiled: June 15, 2021Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes F. Swenberg
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Patent number: 11450759Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: September 30, 2020Date of Patent: September 20, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20220262629Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.Type: ApplicationFiled: April 26, 2022Publication date: August 18, 2022Inventors: Srinivas GANDIKOTA, Yixiong YANG, Jacqueline Samantha WRENCH, Yong YANG, Steven C. H. HUNG
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Patent number: 11417517Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.Type: GrantFiled: November 18, 2020Date of Patent: August 16, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
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Publication number: 20220254640Abstract: A sacrificial sealing layer is formed on a high-K metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-K metal oxide layer on the interfacial layer, the high-K metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-K metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-K metal oxide layer to form a dipole region.Type: ApplicationFiled: June 15, 2021Publication date: August 11, 2022Applicant: Applied Materials, Inc.Inventors: Yong Yang, Jacqueline S. Wrench, Yixiong Yang, Jianqiu Guo, Seshadri Ganguli, Steven C.H. Hung, Srinivas Gandikota
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Publication number: 20220254900Abstract: A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-? metal oxide layer on the interfacial layer, the high-? metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-? metal oxide capping layer on the high-? metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-? metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-? metal oxide layer to form a dipole region.Type: ApplicationFiled: February 8, 2022Publication date: August 11, 2022Applicant: Applied Materials, Inc.Inventors: Yong Yang, Srinivas Gandikota, Steven C.H. Hung, Mandyam Sriram, Jacqueline S. Wrench, Yixiong Yang