Patents by Inventor Steven C. H. Hung

Steven C. H. Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411373
    Abstract: Methods of forming semiconductor device with fluorine-incorporated metal nitride films are described. A substrate surface is exposed to a metal fluoride precursor to form a metal-fluorine species on the substrate surface. The substrate surface is exposed to a nitriding agent to react with the metal-fluorine species to form a fluorine-incorporated metal nitride film.
    Type: Application
    Filed: June 28, 2020
    Publication date: December 31, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Yixiong Yang, Srinivas Gandikota, Steven C.H. Hung, Jacqueline S. Wrench, Yongjing Lin, Susmit Singha Roy, Wei V. Tang, Shih Chung Chen
  • Publication number: 20200373200
    Abstract: A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal, the metal cap comprising one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 26, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Steven C.H. Hung, Srinivas D. Nemani, Yixiong Yang, Susmit Singha Roy, Nikolaos Bekiaris
  • Publication number: 20200373404
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitriride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).
    Type: Application
    Filed: May 18, 2020
    Publication date: November 26, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M. Bernal Ramos, Luping Li, Shih Chung Chen, Jacqueline S. Wrench, Yixiong Yang, Steven C.H. Hung, Srinivas Gandikota, Naomi Yoshida, Lin Dong
  • Publication number: 20200357629
    Abstract: A method of forming an electronic device is disclosed. The method comprises forming a barrier layer on a silicon layer, and depositing a silicon oxide layer on the barrier layer. The formation of the barrier layer on the silicon layer minimizes parasitic oxidation of the underlying silicon layer and minimizes defects in the silicon layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: November 12, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Johanes F. Swenberg, Steven C.H. Hung
  • Publication number: 20200075332
    Abstract: A method of forming a silicon cap which comprises substantially no germanium atoms nor oxygen atoms is disclosed. Methods for controlling the oxidation of a silicon cap layer are also disclosed. Methods of forming a metal gate replacement which utilize the disclosed silicon cap and controlled oxidation are also disclosed.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Johanes F. Swenberg, Abhishek Dube, Steven C.H. Hung, Benjamin Colombeau
  • Patent number: 10510545
    Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process, or a single-step plasma hydrogenation and nitridization process, is performed on a metal nitride layer in a film stack, thereby, according to some embodiments, removing oxygen atoms disposed within layers of the film stack and, in some embodiments, adding nitrogen atoms to the layers of the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 17, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Houda Graoui, Johanes S. Swenberg, Wei Liu, Steven C. H. Hung
  • Patent number: 10431466
    Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 1, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Johanes S. Swenberg, Wei Liu, Houda Graoui, Steven C. H. Hung
  • Publication number: 20190287805
    Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 19, 2019
    Inventors: Steven C. H. HUNG, Johanes S. SWENBERG, Wei LIU, Houda GRAOUI
  • Patent number: 10347492
    Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Johanes S. Swenberg, Wei Liu, Houda Graoui
  • Publication number: 20180218911
    Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.
    Type: Application
    Filed: January 18, 2018
    Publication date: August 2, 2018
    Inventors: Steven C. H. HUNG, Johanes S. SWENBERG, Wei LIU, Houda GRAOUI
  • Patent number: 9748354
    Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: August 29, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei V. Tang, Paul F. Ma, Steven C. H. Hung, Michael Chudzik, Siddarth Krishnan, Wenyu Zhang, Seshadri Ganguli, Naomi Yoshida, Lin Dong, Yixiong Yang, Liqi Wu, Shih Chung Chen
  • Publication number: 20170179252
    Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 22, 2017
    Inventors: Wei V. TANG, Paul F. MA, Steven C. H. HUNG, Michael CHUDZIK, Siddarth KRISHNAN, Wenyu ZHANG, Seshadri GANGULI, Naomi YOSHIDA, Lin DONG, Yixiong YANG, Liqi WU, Shih Chung CHEN
  • Patent number: 9437640
    Abstract: Backside illuminated sensors and methods of manufacture are described. Specifically, a backside illuminated sensor with a dipole modulating layer near the photodiode is described.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 6, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Sherry Mings, Patricia M. Liu, Steven C. H. Hung
  • Patent number: 9275853
    Abstract: Embodiments of the disclosure generally relate to methods of adjusting transistor flat band voltage, and transistor gates formed using the same. In one embodiment, a method sequentially includes cleaning a substrate, annealing the substrate in a nitrogen-containing environment to form silicon-nitrogen bonds, hydroxylating the substrate surface, and depositing a hafnium oxide layer over the substrate. In another embodiment, the method further includes depositing an aluminum oxide layer over the substrate prior to depositing the hafnium oxide layer, and then annealing the substrate.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 1, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tatsuya Sato, Steven C. H. Hung, Eran Newman
  • Publication number: 20150069476
    Abstract: Backside illuminated sensors and methods of manufacture are described. Specifically, a backside illuminated sensor with a dipole modulating layer near the photodiode is described.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 12, 2015
    Inventors: Sherry Mings, Patricia M. Liu, Steven C.H. Hung
  • Publication number: 20150031196
    Abstract: Embodiments of the disclosure generally relate to methods of adjusting transistor flat band voltage, and transistor gates formed using the same. In one embodiment, a method sequentially includes cleaning a substrate, annealing the substrate in a nitrogen-containing environment to form silicon-nitrogen bonds, hydroxylating the substrate surface, and depositing a hafnium oxide layer over the substrate. In another embodiment, the method further includes depositing an aluminum oxide layer over the substrate prior to depositing the hafnium oxide layer, and then annealing the substrate.
    Type: Application
    Filed: July 28, 2014
    Publication date: January 29, 2015
    Inventors: Tatsuya SATO, Steven C. H. HUNG, Eran NEWMAN
  • Patent number: 7541650
    Abstract: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 2, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Gary E. Miner
  • Publication number: 20080142893
    Abstract: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.
    Type: Application
    Filed: October 9, 2007
    Publication date: June 19, 2008
    Inventors: Steven C. H. Hung, Gary E. Miner
  • Patent number: 7317229
    Abstract: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: January 8, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Gary E. Miner
  • Publication number: 20070018244
    Abstract: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 25, 2007
    Inventors: Steven C. H. Hung, Gary E. Miner