Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

Abstract: Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a thermal treatment chamber coupled with the first transfer chamber. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a metal deposition chamber coupled with the second transfer chamber.

Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 ? to less than or equal to 50 ?. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-? metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.

Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.

Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-? gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-? gate dielectric layer.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 ? to less than or equal to 50 ?. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-? metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Abstract: A method of forming an electronic device is disclosed. The method comprises forming a barrier layer on a silicon layer, and depositing a silicon oxide layer on the barrier layer. The formation of the barrier layer on the silicon layer minimizes parasitic oxidation of the underlying silicon layer and minimizes defects in the silicon layer.

Abstract: Methods of forming semiconductor device with fluorine-incorporated metal nitride films are described. A substrate surface is exposed to a metal fluoride precursor to form a metal-fluorine species on the substrate surface. The substrate surface is exposed to a nitriding agent to react with the metal-fluorine species to form a fluorine-incorporated metal nitride film.

Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.

Abstract: A method of forming a semiconductor structure includes pre-cleaning a surface of a substrate, forming an interfacial layer on the pre-cleaned surface of the substrate, depositing a high-? dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms in the deposited high-? dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-? dielectric layer.

Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process, or a single-step plasma hydrogenation and nitridization process, is performed on a metal nitride layer in a film stack, thereby, according to some embodiments, removing oxygen atoms disposed within layers of the film stack and, in some embodiments, adding nitrogen atoms to the layers of the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift.

Abstract: Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.

Abstract: A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.