Abstract: Methods and systems for collaborative coexistence of Bluetooth and WiMax are disclosed. Aspects of one method may include a packet traffic arbiter (PTA) in a mobile terminal that arbitrates among requests to transmit from one or more communication devices collocated in the mobile terminal. The communication devices may comprise, for example, a WLAN communication device, a WiMax communication device, and/or a Bluetooth communication device. The arbitration may be based on, for example, whether a packet will be received by one of the plurality of collocated communication devices at a time of transmission of the present data packet and/or a priority for data to be transmitted. An exemplary scenario may be where a Bluetooth headset may be used for communication over a WiMax voice connection. One arbitration method may comprise allowing the WiMax packet to be transmitted, and replacing the received Bluetooth packet with data indicating silence.

Abstract: An integrated circuit radio transceiver and associated method comprises a multi-mode device operable to support personal area network communications as well as traditional wireless local area network communications. In one embodiment, IEEE 802.11 protocol IBSS communications are used to transport Bluetooth communication data packets. Thus, the multi-mode device is operable to establish traditional BSS communications with an Access Point in addition to establishing peer-to-peer communications with another multi-mode device to transport the Bluetooth communications over the 802.11 IBSS communication link.

Abstract: Driving schemes are described in which rows (1 to m) are selected one at a time and column data voltages are inverted to provide inversion schemes for display devices comprising pixels (12) arranged in rows (1 to m) and columns (1 to n). The order in which rows are selected is such that a first group of first polarity rows is selected in a first order, a first group of second polarity rows is selected in a second order, a second group of first polarity rows is selected in the second order, and a second group of second polarity rows is selected in the first order, the first order being one of ascending or descending row number order, and the second order being the other of ascending or descending row number order.

Abstract: Each stage of a shift register circuit has a first input (Rn?1) connected to the output of the preceding stage, a drive transistor T(drive) for coupling a first clocked power line voltage (Pn) to the output (Rn) of the stage, a compensation capacitor (C1) for compensating for the effects of a parasitic capacitance of the drive transistor, a first bootstrap capacitor (C2) connected between the gate of the drive transistor and the output (Rn) of the stage; and an input transistor (Tin1) for charging the first bootstrap capacitor (C2) and controlled by the first input (Rn?1). Each stage has an input section (10) coupled to the output (Rn?2) of the stage two stages before the stage having a second bootstrap capacitor (C3) connected between the gate of the input transistor (Tin1) and the first input (Rn?1). The use of two bootstrapping capacitors makes the circuit less sensitive to threshold voltage levels or variations, and enables implementation using amorphous silicon technology.

Abstract: Methods for exchanging signals via a network with nodes (11-15) improve the performance of the network by letting a destination node (12) receive the signals originating from a source node (11) via different first and second signal routes, and by processing and correlating these signals in the destination node (12). In dependence of a correlation result, a process for processing a signal in a node (11-15) is adjusted. This process may be situated in the destination node (12), or in the source node (11) or an intermediate node (13-15), in which case a control signal is to be exchanged. A learning algorithm for the adjusting of the process can be run in the nodes (11-15). Label switched routing can be introduced, whereby the label signal is sent from the source node (11) to the destination node via a third signal route different from the first and second signal route, to improve the efficiency of the nodes (11-15).

Abstract: A display controller (40), comprising: a processor (62) for providing row selection pulses (52, 54, 56) for a display comprising M rows of pixels, the row selection pulses (52, 54, 56) having respective durations (t1, t2, t3 . . . tM) that increase from the pulse (52) for row 1 to the pulse (56) for row M. The processor (62) may retime image data (72) for synchronisation with the increase in the pulse duration, for example by writing incoming data (72) in to a buffer (64) at the rate the incoming data (72) is received and reading the data out from the buffer (64) at a rate corresponding to the increase in the pulse duration. Also described is a display device comprising the display controller (40), and a method of driving the display device using the display controller (40). The increase in row selection pulse duration (t1, t2, t3 . . . tM) is arranged to correspond, with a desired level of precision, to an increasing charging time of the pixels of the rows.

Abstract: An active matrix display device has column address circuitry for generating pixel drive signals. The column address circuitry has an output buffer for providing a pixel drive signal to a column conductor, and the positive and negative slew rates of the output buffer are different. By selecting the positive and negative slew rates independently in the design of the output buffer, the size of the transistors (54, 56), particularly those which pass the charging (or discharging) current of the column capacitance, can be kept to a minimum.

Abstract: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN diode. This avoids the exposure of the amorphous silicon to high temperature processing. The TFT comprises doped source/drain regions (16a,17a), one of which (17a) may also provide the ntype or p-type doped region for the diode. Advantageously, the requirement to provide a separate doped region for the photodiode is removed, thereby saving processing costs. A second TFT (10b) having a doped source/drain region (16b,17b) of the opposite conductivity type may provide the other doped region (16b) for the diode, wherein the intrinsic region (25) is disposed laterally between the two TFTs, overlying each of the respective polysilicon islands.

Abstract: An active matrix display device has an array of oled display pixels (2) operable in two modes in which the power supply line (26) is modulated between a low voltage and a normal power supply voltage. In a first mode, a pixel drive transistor current is supplied to the display element (2) and is selected to provide a desired pixel brightness. In a second mode, a voltage is provided to the drive transistor and is selected to provide a desired ageing effect, but no current flows through the display element. The frame time is thus divided into two periods, one when the power supply line (26) is supplied with a voltage of e.g. OV or ?5V to turn the display element on and the other when the power supply line (26) is supplied with a voltage of e.g. OV or ?5V to turn the display element off.

Abstract: In an active matrix display, each pixel has a storage capacitor for storing a voltage to be used for addressing a drive transistor. A discharge transistor is provided for discharging the storage capacitor thereby to switch off the drive transistor. The timing of this is controlled by a light-dependent device which is illuminated by the display element. The drive transistor is controlled to provide a constant light output from the display element, and the duration is controlled in dependence on the data voltage. Optical feedback is used to alter further the timing of operation of the discharge transistor to provide ageing compensation of the display element and compensation for changes in the drive transistor.

Abstract: A method and apparatus for estimating the presence of RF interference in a wireless data channel is described. The method and apparatus comprises a set of identical tracking/register (T/R) filter blocks, each T/R filter block associated and corresponding to an RF channel of interest. Each T/R filter block includes a pair of tracking/register (T/R) filters. Power/magnitude estimates from an RSSI calculation are input to the T/R filter blocks. One T/R filter is used to estimate the noise floor (in the absence of interference). The T/R filter latches and filters the lowest input values received from a power/magnitude circuit. The other T/R filter estimates the level of an interferer, if present, by latching and filtering the largest valued outputs of the power/magnitude circuit.

Abstract: An active matrix display is provided with conductor lines (62a, 62b, 62c) extending along edges of the display over the display substrate but outside the display area (63). These conductor lines comprise at least one layer (90) which is additional to the thin film layers defining the array of pixels. Row driver circuitry and/or column driver circuitry has a portion (40,50) provided on the common substrate outside the display area (63) and which connects to the conductor lines. A dedicated process can be used for the conductor lines in order to form a low resistance lines. These assist in the integration or mounting of row or column driver circuits onto the common substrate.

Abstract: A display device has pixels 41 arranged in rows and columns 42,44 addressed by a grid of first and second addressing conductors 50,52. The addressing conductors 50,52 are not parallel with the pixel rows or pixel columns 42,44. This arrangement decouples the row and columns of pixels from the addressing conductors. This provides freedom in the positioning of the driver circuits, which are positioned at the ends of the first and second conductors, which in turn gives greater design freedom for the shape and position of the display in a product.

Abstract: A method is provided of determining the pixel drive signals to be applied to the pixels of an array of light emitting display elements arranged in rows and columns, with a plurality of the pixels in a row being supplied with current simultaneously along a respective row conductor. Target pixel drive currents are determined from a model of the pixel current-brightness characteristics. These are modified to take account of the voltage on the respective row conductor at each pixel resulting from the currents drawn from the row conductor by the plurality of pixels and the dependency of the pixel brightness characteristics on the voltage on the row conductor at the pixel. This addresses the problem of horizontal cross-talk that occurs in active matrix 1.RD displays due to the finite output impedance of the current providing TFT's as well as the finite resistance of metals used to form power supply lines.

Abstract: A display device has a plurality of pixels, each pixel having a current-driven display element (2) coupled between a first conductive layer (28) and a second conductive layer (27), the second conductive layer (27) being coupled to a current supply (26) via a switchable device (12) having a thin film component (122) on a first area of a substrate (120). Each pixel further has a first capacitive device having a first capacitor plate (132) on a second area of the substrate (120), the first capacitor plate (120) being conductively coupled to the thin film component, a second capacitor plate (133) and a first insulating layer (130) between the first capacitor plate (132) and the second capacitor plate (133).

Abstract: Each pixel of an active matrix electroluminescent display device has a first amorphous silicon drive transistor for intermittently driving a current through the display element and a second amorphous silicon drive transistor for intermittently driving a current through the display element. The aging effect of amorphous silicon TFTs can be reduced by sharing the driving of the display element between two drive transistors. Providing a duty cycle reduces the on-time for each drive transistor, but also provides a period during which there can be some recovery of the TFT characteristics.

Abstract: In an active matrix display device, particularly an AMLCD, having an array of display pixels (8) and comprising pixel electrodes (16), associated switches (22), and address lines (18, 20) carried on a first substrate (10), a common electrode (26) carried on a second substrate (12), a drive circuit (40, 80) carried on the first substrate (10) including at least one conductor line (96) providing a drive voltage for the common electrode (26) and to which the common electrode (26) is connected (92), the common electrode (26) on the second substrate is utilised to provide also electrical connection between the one conductor line (96) and at least one other circuit element (37) carried on the first substrate (10). The use of the common electrode in this way assists in avoiding problems due to resistances of connections formed on the first substrate. The connection to a storage capacitor line (37, 36) may benefit especially.

Abstract: An active matrix display device, particularly a liquid crystal display device, having an array of display pixels (25) driven with inverting polarity drive voltages includes correction means (40, 55) for providing a measurement indicative of a DC voltage level at the pixels (25), for example caused by kickback effects, and modifying pixel drive voltages accordingly so as to compensate for any display artefacts. The correction means includes a plurality of measurement pixels (40), each comprising one or more dummy display pixels, which are arranged at spaced locations along at least one side of the pixel array (45) and which supply independent measurements indicative of the behaviour of display pixels in their neighbourhood. The correction means is then able, for example, to account for variations in pixel DC levels over the array.

Abstract: An IC arrangement (200) has a plurality of IC modules (220a, 220b), the individual IC modules (220a, 220b) being coupled between a first power line (202) and a second power line (204) via a voltage generator (240a, 240b). The voltage generators (240a, 240b) are powered via the first power line (202) and the second power line (204) and are arranged to regenerate a reference voltage on a reference power line (106) for providing the IC modules (220a, 220b) with the regenerated voltage on respective internal power lines (222a, 222b). A feedback loop (242a, 242b) from the internal power lines (222a, 222b) to the voltage generator (240a, 240b) ensures that the voltage on the internal power lines (222a, 222b) remains substantially constant, even if substantial current fluctuations on the first power line (202), the second power line (204) or the internal power line (222a, 222b) occur. The IC arrangement (200) is particularly suitable as a driver circuit for a matrix array device.

Abstract: A portable electronic device (40) comprises a display module (42) and a battery unit (44). The device has at least one further analogue input or output interface (50,52,54) (in addition to the display). The display module includes a voltage converter (48) for providing at least one voltage exceeding the battery unit voltage, and an output from the voltage converter (48) of the display module is provided to a circuit (50a, 52a, 54a) associated with the at least one further analogue input or output interface. This enables a reduction in cost and volume of the device by providing a highly integrated solution, in which a voltage converter within a display module is used also for circuitry of another interface or interfaces.