Abstract: Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the operational characteristic satisfies a low threshold and a high threshold. If the operational characteristic does satisfy the low threshold, the solid state drive throttles high power memory accesses requests while not throttle low power memory access requests. If the operational characteristic satisfies a high threshold, the solid state drive is configured to throttle all memory accesses. The operational characteristic may be embodied as, for example, a temperature of the solid state drive.

Abstract: Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the operational characteristic satisfies a low threshold and a high threshold. If the operational characteristic does satisfy the low threshold, the solid state drive throttles high power memory accesses requests while not throttle low power memory access requests. If the operational characteristic satisfies a high threshold, the solid state drive is configured to throttle all memory accesses. The operational characteristic may be embodied as, for example, a temperature of the solid state drive.

Abstract: Apparatus and methods of reducing power consumption in solid-state disks (SSDs) that can reduce power levels in SSDs below levels achievable in known SSD reduced power states. The apparatus is a power management subsystem operative to detect whether an SSD subsystem has been enabled to enter a reduced power state, and to receive a control signal from a host directing the power management subsystem to place the SSD subsystem in the reduced power state. In the event the SSD subsystem is enabled to enter the reduced power state and the host asserts the control signal, the power management subsystem effectively disconnects at least a portion of the SSD subsystem from the power rail. In the event power-up clear circuitry asserts a clear signal to the power management subsystem, or the host negates the control signal, the power management subsystem reestablishes the connection between the SSD subsystem and the power rail.

Abstract: A protocol provides authentication of peripheral devices by a computing device to which the peripheral device connects. Computing devices include a verifier with a public key that authenticates multiple associated private keys. Private keys are embedded on peripheral devices. When the verifier is able to authenticate a connected peripheral, particular functionality is enabled that may not be enabled for peripherals that do not authenticate.

Abstract: A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor.

Abstract: Apparatus and methods of reducing power consumption in solid-state disks (SSDs) that can reduce power levels in SSDs below levels achievable in known SSD reduced power states. The apparatus is a power management subsystem operative to detect whether an SSD subsystem has been enabled to enter a reduced power state, and to receive a control signal from a host directing the power management subsystem to place the SSD subsystem in the reduced power state. In the event the SSD subsystem is enabled to enter the reduced power state and the host asserts the control signal, the power management subsystem effectively disconnects at least a portion of the SSD subsystem from the power rail. In the event power-up clear circuitry asserts a clear signal to the power management subsystem, or the host negates the control signal, the power management subsystem reestablishes the connection between the SSD subsystem and the power rail.

Abstract: A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor.

Abstract: A protocol provides authentication of peripheral devices by a computing device to which the peripheral device connects. Computing devices include a verifier with a public key that authenticates multiple associated private keys. Private keys are embedded on peripheral devices. When the verifier is able to authenticate a connected peripheral, particular functionality is enabled that may not be enabled for peripherals that do not authenticate.

Abstract: A protocol provides authentication of peripheral devices by a computing device to which the peripheral device connects. Computing devices include a verifier with a public key that authenticates multiple associated private keys. Private keys are embedded on peripheral devices. When the verifier is able to authenticate a connected peripheral, particular functionality is enabled that may not be enabled for peripherals that do not authenticate.

Abstract: A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor.

Abstract: A protocol provides authentication of peripheral devices by a computing device to which the peripheral device connects. Computing devices include a verifier with a public key that authenticates multiple associated private keys. Private keys are embedded on peripheral devices. When the verifier is able to authenticate a connected peripheral, particular functionality is enabled that may not be enabled for peripherals that do not authenticate.

Abstract: A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor.

Abstract: An integrated circuit chip comprises firmware non-volatile memory to store firmware and at least one hardware security primitive device comprising non-volatile memory. The firmware non-volatile memory and the at least one hardware security primitive device are integrated on the integrated circuit chip.

Abstract: A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.

Abstract: A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: According to one embodiment, a programmable random bit source is disclosed. The programmable random bit source includes a latch having a data input, a bias input and a clock input. In addition, the programmable random bit source includes a programmable voltage source coupled to the bias input of the latch and a first oscillator coupled to the data input of the latch to output a first oscillating signal. Further, the programmable random bit source includes a second oscillator coupled to the clock input of the latch circuit to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

Abstract: A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator includes interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A system and method for controlling power are described. A computer system including a memory module and a random number generator is monitored. The random number generator is enabled to generate and process random bits. The memory module is enabled to receive and store the random bits generated. The memory module is then disabled.