Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: A voltage Vpp is provided for use in programing and erasing transistors which transistors normally switch with a voltage Vpp centering at X volts in a range varying from X plus Y to X minus Y volts. When transistors in an array are selected to operate in this range, a significant number of the blocks of memory transistors require as much as three times as long to program and erase as do typical memory transistors. The invention provides circuitry for furnishing a voltage Vpp to program and erase the blocks of the memory array which voltage is controlled to be in a range of X to X+Y volts and centers around X+1/2 Y volts.

Abstract: A memory system contains a plurality of memory cells, a sensing circuit, and a translator circuit. The memory cells store one of a plurality of threshold levels, wherein the threshold levels demarcate windows for designating more than a single bit of data for each memory cell. The sensing circuit, coupled to the memory cells, generates at least one binary coded bit from the threshold level sensed. A translator circuit translates the binary coded bits to gray coded bits such that only one bit changes state between adjacent threshold levels. Because of this, a decrease from one threshold level to a lower adjacent threshold level in a memory cell results in the change of only a single bit of data, thus improving the memory system reliability. The memory system also includes the ability to store threshold states in either a multi-level cell mode or a standard level cell mode. In the standard cell mode, the translator circuit directly passes the binary coded bits without performing any translation.

Abstract: A method for utilizing a cyclical redundancy check value with an identification field stored in memory which is constantly changing between testing of the cyclical redundancy check value. In order to allow the use of a cyclical redundancy check value with a field which constantly varies as does the field in a flash EEPROM memory array, various portions of the field are masked to the cyclical redundancy check and additional reliability checks are utilized to assure that those portions which are masked remain reliable.

Abstract: A circuit for testing the data failure rate of a flash memory array comprising apparatus for writing a test pattern to a memory array; and apparatus positioned in a data path prior to the interface between the memory array and circuitry external to the memory array for detecting differences in data read from the memory array and the test pattern written to the memory array, the last mentioned apparatus including apparatus for reading data from the memory array, apparatus for comparing the value of data read from the memory array with the value of data written to the array in the test pattern, and apparatus for storing a indication that a comparison has produced a result indicating a failure to compare.

Abstract: A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.

Abstract: A process for releasing sectors of a flash EEPROM memory array which includes a plurality of individually erasable blocks and stores sectors of data in such blocks with a header providing a logical sector number, an indication of validity of data stored, and an indication of whether data is stored with the header. The process includes the steps of finding the header of a sector with data to be released, setting the indication of validity of the data stored to indicate that the data is invalid, and writing a new header for the sector to a new position in the array without data and with an indication that data is not attached.

Abstract: A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.

Abstract: In a process for cleaning up a flash EEPROM memory array separated into blocks which may be separately erased, in which process all valid data is first written to other blocks of the array, and then the block is erased, the improvement including the step of determining a block to clean up based on a comparison of the number of invalid sectors each block includes and the number of switching operations which each block has undergone.

Abstract: Circuitry for preventing slow erasing and slow programming in non-volatile semiconductor memories is disclosed. This circuitry establishes the potential on the source regions of cells in blocks not currently being programming so as to substantially prevent the occurrences of slow erasing and slow programming which can alter the state or condition of the cells.

Abstract: Circuitry for discharging a drain of a cell of a non-volatile semiconductor memory is described. A discharge transistor is coupled between (1) the drain of the cell and (2) ground for selectably (a) providing a discharge paths to ground for the drain of the cell when the discharge transistor is enabled and (b) not providing a discharge path to ground for the drain of the cell when the discharge transistor is not enabled. Circuitry is coupled to the discharge transistor for enabling the discharge transistor for a duration that both begins and ends (1) after a first operation is performed with respect to the cell and (2) before a verify operation is performed with respect to the cell.

Abstract: A blocking architecture for use in non-volatile semiconductor memories is disclosed. This architecture minimizes device area taken up by signal lines while maximizing device yield. Additionally, this architecture minimizes the Y decoding mechanism while maximizing device performance.