Abstract: A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A random number generator includes a random bit source to generate random bits and circuitry to process the generated random bits to accumulate entropy in the generated random bits. The random number generator also includes circuitry to output processed random bits selectively such that at least one processed random bit is not output.

Abstract: A method and apparatus for producing a corrected bit stream from a random bit stream output by a random bit source. Sequential pairs of bits in the random bit stream are compared. If both bits in a pair of bits are identical, the output bits are discarded. If both bits in a pair of bits are different, one bit of the pair of bits is taken as the output bit.

Abstract: A method for calibrating analog sensor measurements within a computer system is disclosed. The method includes the steps of generating an analog sensor measurement result, reading at least two values that define a curve from a memory device, and calculating a calibrated result using the analog sensor measurement result and the values that define the curve.

Abstract: An integrated circuit chip comprises firmware non-volatile memory to store firmware and at least one hardware security primitive device comprising non-volatile memory. The firmware non-volatile memory and the at least one hardware security primitive device are integrated on the integrated circuit chip.

Abstract: A system and method of implementing a digit counter having a plurality of digits, ranging from a least significant digit (LSD) to a maximum positional digit (MDP), is described. In one embodiment, the system comprises switching a single digit for each increment from the LSD to the MPD. Further, after the MPD is switched, for the next increment, resetting the digits from the LSD to the MPD, and moving the LSD and the MPD by one digit, such that the original LSD becomes a higher precedence digit.

Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Abstract: A circuit for selecting a select line from a plurality of first and second select lines is described. Each of an array of integrated circuit (IC) packages is coupled to (1) one of the first select lines and (2) at least one of the second select lines. The circuit includes a decoder for decoding a select data to select the select line, and circuitry for modifying the select data before the select data is applied to the decoder when each of the second select lines is not coupled to an IC device within each of the IC packages to ensure that the select line is not one of the second select lines. When each of the first and second select lines is coupled to an IC device within each of the IC packages, the circuitry for modifying does not modify the select data. A method for selecting a selected IC device within a selected IC package of an array of IC packages is also described.

Abstract: A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Abstract: A method for managing and addressing an executable-in-place (XIP) program stored in a memory having a plurality of blocks includes the step of virtually storing a first portion of the XIP program in a first page of a paged virtual memory space and a second portion of the XIP program in a second page of the paged virtual memory space. The first portion of the XIP program is physically stored in a first block of the plurality of blocks and the second portion of the XIP program is physically stored in a second block of the plurality of blocks. A memory address mapping window is established with addresses of the first block. A page map for mapping the memory address mapping window to the first page is established. The first block is addressed for the first portion of the XIP program via the page map and the memory address mapping window.

Abstract: A controller for controlling associated circuitry which includes a microprocessor, read only memory for storing control processes to be run by the microprocessor for controlling the associated circuitry, random access memory, and means for accessing the associated circuitry, by a process which detects changes in the associated circuitry during operation of the associated circuitry, and writes those changes to the read only memory so that they are available to the controller should power be lost during the operation of the associated circuitry.

Abstract: A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.

Abstract: A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.

Abstract: A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which each of the blocks of memory cells has stored thereon data regarding management of the array during a cleanup process in which valid data stored in a first block is written to another block of the array, and then the first block is erased. The process includes the steps of storing data regarding management of the array from the first block in random access memory and, in an enhanced process, on another block before erasure of the first block. The data may then be rewritten to the first block after the erase.

Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode.

Abstract: A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.

Abstract: A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode.