Abstract: A combination cabinet and drawer construction includes a catch associated with the drawers that is cooperative with a biased, releasable locking bar. The locking bar is responsive to a cylinder lock actuated by a rod that engages the locking bar and rotates the bar to move it out of engagement with a leg of a drawer catch thereby releasing the drawer.

Abstract: A vehicle wheel hub bearing unit comprises:a stationary, radially outer race having a portion projecting radially outwardly;a rotatable, radially inner race;an encoder fixed for rotation with the rotatable radially inner race in close proximity to the inboard side of a flange fast for rotation with the hub and projecting radially outwardly therefrom;a sensor mount element fixed to the radially outwardly projecting portion;a sensor body mounted in removable manner to the mount element and incorporating a sensor element facing in operation the encoder.

Abstract: A method of retaining and dispensing a detergent tablet in an automatic washing machine. The method includes the step of providing a dispensing device having a flexible and resilient cage structure which is liquid permeable. Another step is flexibly deforming the cage structure and inserting the detergent tablet in the cage structure such that said detergent tablet is retained therein. Yet another step is placing the dispensing device including the detergent tablet into an automatic washing machine for a washing cycle in which a wash liquor is caused to pass through the cage structure to progressively dissolve and dispense detergent from the detergent tablet.

Abstract: A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.

Abstract: An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.

Abstract: A tool box includes a bin section for receipt of tools, trays and removable containers or compartments. A hinged lid fits onto the bin portion of the tool box and is designed to retain the various containers and trays in position when closed. The area of the lid is enclosed within the profile of the base of the bin to facilitate sitting and standing thereon and to increase stability of the assembly.

Abstract: An error suppressing circuit (301) and method therefor for a phase locked loop (PLL) (300). According to one embodiment of the present invention, a transient condition, for example, a bandwidth switch, in the PLL (300) is detected. The PLL (300) is opened for a period of time (509) responsive to detecting the transient condition. The phase of a reference frequency signal (115) and the phase of a output frequency signal (116 or 117) are synchronized after a lapse of the period of time (509). The PLL (300) is closed responsive to the phase of the reference frequency signal (115) and the phase of the output frequency signal (116 or 117) being synchronized. The present envention advantageously reduces the length of time it takes for the PLL (300) to correct for the phase and frequency error generated by the transient condition, and is capable of operating with various types of PLLs.

Abstract: Internal combustion engine cylinder compression ratio measurement is provided by applying a train of pressure pulses to an engine cylinder, measuring time rate of change in pressure within the cylinder and estimating a volume of air within the cylinder from the measured time rate of change. The cylinder air volume may be compensated for such effects as change in cylinder air temperature away from a calibration temperature or cylinder leakage. The time rate of change in pressure is measured at an engine angular position corresponding to a known volume within the cylinder, for example an engine angular position corresponding to the cylinder top dead center position, and cylinder compression ratio is determined from the estimated volume of air in the cylinder and the known cylinder volume.

Abstract: A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.