Abstract: A novel design and method of fabricating a semiconductor device. In a preferred embodiment, the present invention is a flip chip package including a BT substrate. On the side of the substrate facing the die, thin traces are formed of an enhanced conductive material. Conductive bumps such as eutectic solder balls are then mounted on the traces, and the die mounted to the bumps. The die then packaged and mounted to a printed circuit board using, for example, a ball grid array.

Abstract: A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.

Abstract: In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.

Abstract: A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.

Abstract: A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.

Abstract: A venous-arterial detector is disclosed. The detector includes a first chamber in fluid communication with a needle, and an indicator chamber in selective fluid communication with the first chamber through a valve. The indicator chamber is pre-pressurized to a defined pressure that preferably exceeds typical venous pressure, and the valve retains that pressure within the indicator chamber. When the needle is inserted into a vessel, if the pressure in the vessel is greater than the defined pressure in the indicator chamber, blood will flow into the indicator chamber, indicating that the vessel is most likely to be an artery.

Abstract: Disclosed herein are memory circuit embodiments to have spatially encoded data.

Abstract: Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

Abstract: A keypad is provided for a computing device. The keypad includes one or more lighting devices or mechanisms for illuminating a plurality of keys structures. In an embodiment, the plurality of key structures are formed from a milky material.

Abstract: A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: A sense amplifier includes a storage element and logic circuitry to transition encode an output signal.

Abstract: In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

Abstract: A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.

Abstract: A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.

Abstract: A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

Abstract: A device comprising a receiving circuit to receive an input signal, a voltage level converting circuit and a biasing circuit. The receiving circuit including an output and a first latch circuit coupled to a first supply node. The voltage level converting circuit includes a second latch circuit coupled to a second supply node, the second latch circuit including cross-coupled logic gates connected between first and second circuit nodes. The second supply node has a voltage level different from the first supply node. The biasing circuit has an input coupled to the receiving circuit output, and also has first and second outputs connectable to bias the first and second circuit nodes of the second latch circuit to complementary logic states based on the receiving circuit output.

Abstract: A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding scheme for searching the memory. The two or more cells may be consecutive bit positions of a word, and the driver may be synchronously operated to generate the different combinations of values.

Abstract: A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

Abstract: A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.