Patents by Inventor Steven J. Clohset
Steven J. Clohset has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210192829Abstract: A ray-tracing system for performing intersection testing includes a tester module for testing rays for intersection with a volume, the tester module receiving a packet of one or more rays to be tested for intersection with the volume. A first set of one or more testers performs intersection testing at a first level of precision to provide intersection testing results, wherein for a first type of the intersection testing result from the first set of one or more testers intersection testing does not need to be reperformed at a second level of precision greater than the first level of precision, and for a second type of the intersection testing result from the first set of one or more testers intersection testing is to be reperformed at the second level of precision; and a second set of one or more testers configured to perform intersection testing at the second level of precision.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Inventors: Gregory Clark, Steven J. Clohset, Luke T. Peterson, Naser Sedaghati, Ali Rabbani
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Publication number: 20210174572Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Gregory Clark, John W. Howson, Justin DeCell, Steven J. Clohset
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Patent number: 11010956Abstract: Foveated rendering for rendering an image uses a ray tracing technique to process graphics data for a region of interest of the image, and a rasterisation technique is used to process graphics data for other regions of the image. A rendered image can be formed using the processed graphics data for the region of interest of the image and the processed graphics data for the other regions of the image. The region of interest may correspond to a foveal region of the image. Ray tracing naturally provides high detail and photo-realistic rendering, which human vision is particularly sensitive to in the foveal region; whereas rasterisation techniques are suited for providing temporal smoothing and anti-aliasing in a simple manner, and is therefore suited for use in the regions of the image that a user will see in the periphery of their vision.Type: GrantFiled: December 8, 2016Date of Patent: May 18, 2021Assignee: Imagination Technologies LimitedInventors: Steven Blackmon, Luke T. Peterson, Cuneyt Ozdas, Steven J. Clohset
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Publication number: 20210142548Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.Type: ApplicationFiled: December 18, 2020Publication date: May 13, 2021Inventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
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Publication number: 20210134047Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.Type: ApplicationFiled: January 11, 2021Publication date: May 6, 2021Inventors: John W. Howson, Luke Tilman Peterson, Steven J. Clohset
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Patent number: 10970914Abstract: A ray-tracing system configured to perform intersection testing, comprising: a tester module for testing rays for intersection with a volume, the tester module being configured to receive a packet of one or more rays to be tested for intersection with the volume, wherein the tester module comprises: a first set of one or more testers configured to perform intersection testing at a first level of precision to provide intersection testing results, wherein for a first type of the intersection testing result from the first set of one or more testers intersection testing does not need to be reperformed at a second level of precision greater than the first level of precision, and for a second type of the intersection testing result from the first set of one or more testers intersection testing is to be reperformed at the second level of precision; and a second set of one or more testers configured to perform intersection testing at the second level of precision; wherein the tester module is configured to: allocateType: GrantFiled: November 15, 2019Date of Patent: April 6, 2021Assignee: Imagination Technologies LimitedInventors: Gregory Clark, Steven J. Clohset, Luke T. Peterson, Naser Sedaghati, Ali Rabbani
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Patent number: 10964090Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by: traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.Type: GrantFiled: July 9, 2018Date of Patent: March 30, 2021Assignee: Imagination Technologies LimitedInventors: Gregory Clark, John W. Howson, Justin DeCell, Steven J. Clohset
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Publication number: 20210065425Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: Luke T. Peterson, James A. McCombe, Steven J. Clohset, Jason R. Redgrave
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Patent number: 10909745Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.Type: GrantFiled: January 15, 2019Date of Patent: February 2, 2021Assignee: Imagination Technologies LimitedInventors: John W. Howson, Luke Tilman Peterson, Steven J. Clohset
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Patent number: 10902667Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.Type: GrantFiled: May 8, 2020Date of Patent: January 26, 2021Assignee: Imagination Technologies LimitedInventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
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Patent number: 10861214Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.Type: GrantFiled: July 26, 2016Date of Patent: December 8, 2020Assignee: Imagination Technologies LimitedInventors: Luke T. Peterson, James A. McCombe, Steven J. Clohset, Jason R. Redgrave
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Publication number: 20200273234Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
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Patent number: 10657700Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.Type: GrantFiled: November 1, 2017Date of Patent: May 19, 2020Assignee: Imagination Technologies LimitedInventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
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Patent number: 10489962Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by: traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.Type: GrantFiled: August 1, 2019Date of Patent: November 26, 2019Assignee: Imagination Technologies LimitedInventors: Gregory Clark, John W. Howson, Justin DeCell, Steven J. Clohset
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Publication number: 20190355166Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by: traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Inventors: Gregory Clark, John W. Howson, Justin DeCell, Steven J. Clohset
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Patent number: 10417807Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3D scene. A hierarchical acceleration structure may be traversed by: traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.Type: GrantFiled: July 13, 2017Date of Patent: September 17, 2019Assignee: Imagination Technologies LimitedInventors: Gregory Clark, John W. Howson, Justin DeCell, Steven J. Clohset
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Publication number: 20190266782Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventors: John W. Howson, Steven J. Clohset, Ali Rabbani
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Publication number: 20190236834Abstract: Foveated rendering for rendering an image uses a ray tracing technique to process graphics data for a region of interest of the image, and a rasterisation technique is used to process graphics data for other regions of the image. A rendered image can be formed using the processed graphics data for the region of interest of the image and the processed graphics data for the other regions of the image. The region of interest may correspond to a foveal region of the image. Ray tracing naturally provides high detail and photo-realistic rendering, which human vision is particularly sensitive to in the foveal region; whereas rasterisation techniques are suited for providing temporal smoothing and anti-aliasing in a simple manner, and is therefore suited for use in the regions of the image that a user will see in the periphery of their vision.Type: ApplicationFiled: April 9, 2019Publication date: August 1, 2019Inventors: Steven Blackmon, Luke T. Peterson, Cuneyt Ozdas, Steven J. Clohset
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Patent number: 10332303Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.Type: GrantFiled: April 26, 2016Date of Patent: June 25, 2019Assignee: Imagination Technologies LimitedInventors: John W. Howson, Steven J. Clohset, Ali Rabbani
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Publication number: 20190147638Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.Type: ApplicationFiled: January 15, 2019Publication date: May 16, 2019Inventors: John W. Howson, Luke Tilman Peterson, Steven J. Clohset