Patents by Inventor Steven J. Holmes

Steven J. Holmes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226114
    Abstract: Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Brent A. Wacaser, Damon Farmer
  • Publication number: 20210194427
    Abstract: A remotely powered low power oscillator. According to an embodiment of the present invention, a method comprises an oscillator core, in a first environment, generating an oscillating signal; a power management system, in a second environment, supplying power to the oscillator core to operate the oscillator core; a sensing system, in the first environment, sensing one or more parameters of the oscillator core, and generating one or more signals representing said one or more parameters; transmitting the one or more signals from the sensing system to the second environment; and using the one or more signals in the second environment to control the power supplied to the oscillator core from the power management system.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210193897
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Steven J. Holmes, Devendra V. Sadana, Ning Li, Stephen W. Bedell
  • Publication number: 20210175407
    Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Steven J. Holmes, Bruce B. Doris, Matthias Georg Gottwald, Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11025234
    Abstract: Methods and systems for regulating supply voltage is described. In an example, a device can receive unregulated supply. The device can be connected to a ring oscillator and an integrated circuit. The device can be configured to regulate the unregulated supply to a first voltage. The device can be further configured to provide the regulated supply to the ring oscillator, where the ring oscillator operates with the regulated supply. The device can be further configured to, in response to a change in the regulated supply from the first voltage to a second voltage, adjust the changed regulated supply to return to the first voltage to cause the ring oscillator to operate with a constant regulated supply having the first voltage.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11024354
    Abstract: Circuits and methods are disclosed that, in embodiments, may be used for low power memory signal readout. In an embodiment, the circuit comprises a front end stage including an impedance conversion network for receiving a signal and providing voltage or current gain, and a wideband multiplier for receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; and a baseband stage including a voltage mode mixer for receiving the differential output signals from the wideband multiplier and providing voltage gain, and a bandpass filter/amplifier for receiving a mixer output signal from the voltage mode mixer and filtering and amplifying the mixer output signal; and wherein DC voltages of the front-end stage are biased independently of a biasing of DC voltages of the baseband stage.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11013908
    Abstract: A nanodevice includes an array of metal nanorods formed on a substrate. An electropolymerized electrical conductor is formed over tops of a portion of the nanorods to form a reservoir between the electropolymerized conductor and the substrate. The electropolymerized conductor includes pores that open or close responsively to electrical signals applied to the nanorods. A cell loading region is disposed in proximity of the reservoir, and the cell loading region is configured to receive stem cells. A neurotrophic dispensing material is loaded in the reservoir to be dispersed in accordance with open pores to affect growth of the stem cells when in vivo.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Qinghuang Lin, Emily R. Kinser, Nathan P. Marchack, Roy R. Yu
  • Publication number: 20210151658
    Abstract: A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20210151848
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210151575
    Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
  • Publication number: 20210151653
    Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20210143310
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Stephen W. Bedell, Ning Li, Patryk Gumann
  • Publication number: 20210143311
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A reflectrometry wire comprising a second metal within the reflectrometry region is formed. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Ning Li, Stephen W. Bedell, Patryk Gumann
  • Publication number: 20210143312
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Stephen W. Bedell, Sean Hart, Devendra K. Sadana, Ning Li, Patryk Gumann
  • Publication number: 20210135085
    Abstract: A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Inventors: Stephen W. Bedell, Steven J. Holmes, Ning Li, Devendra K. Sadana
  • Publication number: 20210130944
    Abstract: In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Patent number: 10978631
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Ning Li, Stephen W. Bedell
  • Patent number: 10954544
    Abstract: Embodiments of the present invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a semiconductor substrate. The semiconductor device also includes a plurality of metal nanopillars formed on the substrate. The semiconductor device also includes an amperometric sensor associated with one of the plurality of nanopillars, wherein the amperometric sensor is selective to an enzyme-active neurotransmitter. The semiconductor device also includes a resistivity sensor associated with a pair of nanopillars, wherein the resistivity sensor is selective to an analyte.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Steven J. Holmes, Qinghuang Lin, Roy R. Yu
  • Publication number: 20210074903
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Ning Li, Stephen W. Bedell
  • Patent number: 10926079
    Abstract: A nanodevice includes an array of metal nanorods formed on a substrate. An electropolymerized electrical conductor is formed over tops of a portion of the nanorods to form a reservoir between the electropolymerized conductor and the substrate. The electropolymerized conductor includes pores that open or close responsively to electrical signals applied to the nanorods. A cell loading region is disposed in proximity of the reservoir, and the cell loading region is configured to receive stem cells. A neurotrophic dispensing material is loaded in the reservoir to be dispersed in accordance with open pores to affect growth of the stem cells when in vivo.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Qinghuang Lin, Emily R. Kinser, Nathan P. Marchack, Roy R. Yu