Patents by Inventor Steven J. Holmes

Steven J. Holmes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151658
    Abstract: A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20210151653
    Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20210151848
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210151575
    Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
  • Publication number: 20210143312
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Stephen W. Bedell, Sean Hart, Devendra K. Sadana, Ning Li, Patryk Gumann
  • Publication number: 20210143310
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Stephen W. Bedell, Ning Li, Patryk Gumann
  • Publication number: 20210143311
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A reflectrometry wire comprising a second metal within the reflectrometry region is formed. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Ning Li, Stephen W. Bedell, Patryk Gumann
  • Publication number: 20210135085
    Abstract: A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Inventors: Stephen W. Bedell, Steven J. Holmes, Ning Li, Devendra K. Sadana
  • Publication number: 20210130944
    Abstract: In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Patent number: 10978631
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Ning Li, Stephen W. Bedell
  • Patent number: 10954544
    Abstract: Embodiments of the present invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a semiconductor substrate. The semiconductor device also includes a plurality of metal nanopillars formed on the substrate. The semiconductor device also includes an amperometric sensor associated with one of the plurality of nanopillars, wherein the amperometric sensor is selective to an enzyme-active neurotransmitter. The semiconductor device also includes a resistivity sensor associated with a pair of nanopillars, wherein the resistivity sensor is selective to an analyte.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Steven J. Holmes, Qinghuang Lin, Roy R. Yu
  • Publication number: 20210074903
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Ning Li, Stephen W. Bedell
  • Patent number: 10926079
    Abstract: A nanodevice includes an array of metal nanorods formed on a substrate. An electropolymerized electrical conductor is formed over tops of a portion of the nanorods to form a reservoir between the electropolymerized conductor and the substrate. The electropolymerized conductor includes pores that open or close responsively to electrical signals applied to the nanorods. A cell loading region is disposed in proximity of the reservoir, and the cell loading region is configured to receive stem cells. A neurotrophic dispensing material is loaded in the reservoir to be dispersed in accordance with open pores to affect growth of the stem cells when in vivo.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Qinghuang Lin, Emily R. Kinser, Nathan P. Marchack, Roy R. Yu
  • Patent number: 10918852
    Abstract: A nanodevice includes an array of metal nanorods formed on a substrate. An electropolymerized electrical conductor is formed over tops of a portion of the nanorods to form a reservoir between the electropolymerized conductor and the substrate. The electropolymerized conductor includes pores that open or close responsively to electrical signals applied to the nanorods. A cell loading region is disposed in proximity of the reservoir, and the cell loading region is configured to receive stem cells. A neurotrophic dispensing material is loaded in the reservoir to be dispersed in accordance with open pores to affect growth of the stem cells when in vivo.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Qinghuang Lin, Emily R. Kinser, Nathan P. Marchack, Roy R. Yu
  • Patent number: 10903544
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20200397362
    Abstract: A method includes implanting an implantable biosensor within a subject where the implantable biosensor has an array of light sources and an array of light detectors, activating the array of light sources to direct light signals at a targeted tissue site in the subject, capturing, with the light detectors, the light signals reflected off the targeted site, calculating a roundtrip propagation time for each of the light signals and comparing the roundtrip propagation time for each of the light signals against previous calculated respective roundtrip propagation times to determine an occurrence of a change in the targeted tissue site.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell
  • Publication number: 20200380343
    Abstract: Techniques are disclosed for fabricating and using a neuromorphic computing device including biological neurons. For example, a method for fabricating a neuromorphic computing device includes forming a channel in a first substrate and forming at least one sensor in a second substrate. At least a portion of the channel in the first substrate is seeded with a biological neuron growth material. The second substrate is attached to the first substrate such that the at least one sensor is proximate to the biological neuron growth material and growth of the seeded biological neuron growth material is stimulated to grow a neuron in the at least a portion of the channel.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 3, 2020
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Teodor K. Todorov
  • Patent number: 10833685
    Abstract: A voltage controlled oscillator (VCO) circuit and method achieves linearized frequency tuning over an extended range of analog tuning voltage by implementing a magnetic balun/transformer for biasing and coupling varactor elements. An active negative transconductance circuit of cross-coupled transistors have drains connected with a resonant tank circuit and at least a first varactor element having ends connected to respective first ends of respective first coils of a respective first and second magnetic balun. Respective second ends of respective first coils of respective first and second baluns are connected to a first reference supply voltage. A second varactor element has ends connecting respective first ends of respective second coils of said first and second baluns. A sinking of a bias current through the resonant tank circuit and the transconductance circuit generates an oscillating signal. A calibration method achieves precise VCO gain over wide tuning voltage range, thereby enhancing VCO linearity.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20200348256
    Abstract: An electrochemical sensor array includes a thermal oxide configured to interface with one or more analytes. There is a transistor device layer that includes a plurality of field effect transistors (FETs) on top of the thermal oxide. A contact and wiring structure layer is on top of the transistor device layer and operative to couple to control nodes of each of the plurality of FETs. The contact and wiring structure are on a side opposite to that of the thermal oxide.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 5, 2020
    Inventors: Sufi Zafar, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20200343614
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris