Patents by Inventor Steven J. Radigan
Steven J. Radigan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666799Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.Type: GrantFiled: October 31, 2014Date of Patent: May 30, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Naohito Yanagida, Cheng Feng, Michiaki Sano, Akira Nakada, Steven J. Radigan, Eiji Hayashi
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Publication number: 20170040381Abstract: A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Inventors: Yung-Tin Chen, Steven J. Radigan, Roy E. Scheuerlein, Raul Adrian Cernea
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Publication number: 20160126292Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.Type: ApplicationFiled: October 31, 2014Publication date: May 5, 2016Inventors: Naohito Yanagida, Cheng Feng, Michiaki Sano, Akira Nakada, Steven J. Radigan, Eiji Hayashi
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Patent number: 8987802Abstract: A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.Type: GrantFiled: February 28, 2013Date of Patent: March 24, 2015Assignee: SanDisk Technologies Inc.Inventors: Donovan Lee, James Kai, Vinod Purayath, George Matamis, Steven J. Radigan
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Publication number: 20140239365Abstract: A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: Donovan Lee, James Kai, Vinod Purayath, George Matamis, Steven J. Radigan
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Patent number: 8722518Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.Type: GrantFiled: May 9, 2013Date of Patent: May 13, 2014Assignee: SanDisk 3D LLCInventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
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Patent number: 8658526Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.Type: GrantFiled: February 6, 2013Date of Patent: February 25, 2014Assignee: SanDisk 3D LLCInventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
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Patent number: 8637389Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.Type: GrantFiled: January 18, 2013Date of Patent: January 28, 2014Assignee: SanDisk 3D LLCInventors: Yung-Tin Chen, Steven J. Radigan
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Publication number: 20130336037Abstract: A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.Type: ApplicationFiled: March 15, 2013Publication date: December 19, 2013Applicant: SanDisk 3D LLCInventors: Yung-Tin Chen, Steven J. Radigan, Roy E. Scheuerlein, Raul Adrian Cernea
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Publication number: 20130244395Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.Type: ApplicationFiled: May 9, 2013Publication date: September 19, 2013Applicant: SanDisk 3D LLCInventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
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Patent number: 8372740Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.Type: GrantFiled: February 6, 2012Date of Patent: February 12, 2013Assignee: SanDisk 3D, LLCInventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
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Patent number: 8357606Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.Type: GrantFiled: December 20, 2011Date of Patent: January 22, 2013Assignee: SanDisk 3D LLCInventors: Yung-Tin Chen, Steven J. Radigan
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Patent number: 8329512Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: May 3, 2012Date of Patent: December 11, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20120276744Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: ApplicationFiled: May 3, 2012Publication date: November 1, 2012Applicant: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Patent number: 8252644Abstract: A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.Type: GrantFiled: September 8, 2011Date of Patent: August 28, 2012Assignee: SanDisk 3D LLCInventors: Scott Brad Herner, Steven J. Radigan
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Patent number: 8241969Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: August 24, 2011Date of Patent: August 14, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20120135603Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.Type: ApplicationFiled: February 6, 2012Publication date: May 31, 2012Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
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Patent number: 8187932Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.Type: GrantFiled: October 15, 2010Date of Patent: May 29, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
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Publication number: 20120094478Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.Type: ApplicationFiled: December 20, 2011Publication date: April 19, 2012Inventors: Yung-Tin Chen, Steven J. Radigan
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Publication number: 20120091413Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala