Patents by Inventor Steven J. Radigan

Steven J. Radigan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8114765
    Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: February 14, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
  • Publication number: 20110318911
    Abstract: A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.
    Type: Application
    Filed: September 8, 2011
    Publication date: December 29, 2011
    Inventors: S. Brad Herner, Steven J. Radigan
  • Patent number: 8084347
    Abstract: A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 27, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8080443
    Abstract: A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: December 20, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Chun-Ming Wang, Steven J. Radigan
  • Publication number: 20110306174
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Application
    Filed: August 24, 2011
    Publication date: December 15, 2011
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 8071475
    Abstract: A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: December 6, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yoichiro Tanaka, Steven J. Radigan, Usha Raghuram
  • Patent number: 8026178
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: September 27, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 8018025
    Abstract: A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: September 13, 2011
    Assignee: SanDisk 3D LLC
    Inventors: S. Brad Herner, Steven J. Radigan
  • Patent number: 7994068
    Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 9, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Steven J. Radigan, Michael W. Konevecki
  • Patent number: 7982273
    Abstract: A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: July 19, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Christopher J. Petti, Steven J. Radigan, Tanmay Kumar
  • Publication number: 20110171815
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 14, 2011
    Inventors: Natalie NGUYEN, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 7968277
    Abstract: A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: June 28, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Steven J. Radigan, Paul Poon, Michael Konevecki
  • Patent number: 7927977
    Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: April 19, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Raghuveer S. Makala, Vance Dunton, Yoichiro Tanaka, Steven Maxwell, Tong Zhang, Steven J. Radigan
  • Patent number: 7923305
    Abstract: A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, etching the first sacrificial layer using both the first and the second photoresist features as a mask to form first sacrificial features, forming a spacer layer over the first sacrificial features, etching the spacer layer to form spacer features and to expose the sacrificial features, removing the first sacrificial features, and etching at least part of the underlying layer using the spacer features as a mask.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: April 12, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen
  • Publication number: 20110014779
    Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 20, 2011
    Inventors: Raghuveer S. Makala, Vance Dunton, Yoichiro Tanaka, Steven Maxwell, Tong Zhang, Steven J. Radigan
  • Publication number: 20100243602
    Abstract: A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.
    Type: Application
    Filed: June 8, 2010
    Publication date: September 30, 2010
    Inventors: Yung-Tin Chen, Steven J. Radigan, Paul Poon, Michael W. Konevecki
  • Patent number: 7794921
    Abstract: A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: September 14, 2010
    Assignee: Sandisk Corporation
    Inventors: Yung-Tin Chen, Steven J. Radigan, Paul Poon, Michael W. Konevecki
  • Patent number: 7786015
    Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: August 31, 2010
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Chun-Ming Wang, Steven J. Radigan, Christopher J. Petti, Steven Maxwell
  • Publication number: 20100193916
    Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.
    Type: Application
    Filed: April 5, 2010
    Publication date: August 5, 2010
    Applicant: SanDisk 3D LLC
    Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
  • Publication number: 20100181657
    Abstract: A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
    Type: Application
    Filed: June 10, 2009
    Publication date: July 22, 2010
    Applicant: SanDisk 3D LLC
    Inventors: S. Brad Herner, Steven J. Radigan