Abstract: A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.

Abstract: A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Abstract: Metal structures for ICs and methods for manufacturing the same are described. The metal structures range from small features to large features and are resistant to peeling problems during heat treatments that occur during the manufacturing process. Peeling of the metal structures from the underlying structures or substrates is reduced or prevented. The peeling problems are reduced or prevented by including a capping layer or capping structure over the dielectric layer over the metal structure and then annealing the capping layer or capping structure, thereby enhancing the adhesion of the metal structure to the underlying structure or substrate.

Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

Abstract: Metal structures for ICs and methods for manufacturing the same are described. The metal structures range from small features to large features and are resistant to peeling problems during heat treatments that occur during the manufacturing process. Peeling of the metal structures from the underlying structures or substrates is reduced or prevented. The peeling problems are reduced or prevented by including a capping layer or capping structure over the dielectric layer over the metal structure and then annealing the capping layer or capping structure, thereby enhancing the adhesion of the metal structure to the underlying structure or substrate.

Abstract: A process for patterning plasma etchable regions on a semiconductor structure includes the steps of forming a layer of an oxide of aluminum over the surface of the semiconductor structure, forming an overlying layer of plasma etchable material on the layer of oxide, and removing undesired portions of the overlying layer by plasma etching to thereby expose portions of the layer of oxide. In some embodiments of the invention the thereby exposed portions of the layer of oxide are then removed, together with any underlying portions of the first layer, by isotropic etching.