Abstract: Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets.

Abstract: Disclosed is the use of a removable passivating layer in multichip packaging and CUBE applications. The process takes advantage of the fact that various metal ions will react with the carboxylic acid groups of various polyimide precursors. The polyimide will cure at a first temperature and the system may be manipulated and tested. At a later point, the polyimide is subjected to a second, higher temperature in order to decompose or completely destroy the polyimide.

Abstract: A method of making a rim-type phase shift mask comprising the steps of: providing a substrate having opposing first and second surfaces, the first surface being at least partially covered with a first layer of material that substantially blocks the transmission therethrough of electromagnetic radiation of the predetermined range of wavelengths; forming a plurality of openings extending through the first layer so as to expose underlying portions of the first surface of the substrate; depositing a layer of hybrid photoresist on the first layer; exposing the second surface of the substrate to electromagnetic radiation to activate the desired portions of the hybrid photoresist; developing the photoresist, thereby exposing portions underlying the resist; and etching the exposed portions of the substrate is disclosed.

Abstract: Disclosed is the use of a removable passivating layer in multichip packaging and CUBE applications. The process takes advantage of the fact that various metal ions will react with the carboxylic acid groups of various polyimide precursors. The polyimide will cure at a first temperature and the system may be manipulated and tested. At a later point, the polyimide is subjected to a second, higher temperature in order to decompose or completely destroy the polyimide.

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets.

Abstract: A transfer metal configuration and fabrication process possessing increased probability of intersecting a transverse metallization level are presented, without employing an increase in actual metal thickness. The transfer metal is configured with a non-rectangular transverse cross-section such that the thickness of the electrical connect remains the same, but the transverse contact area of the exposed metal is increased. The entire transfer metal may have the same transverse cross-sectional configuration or have portions with different transverse configurations. If different configurations are employed, each portion of the transfer metal to be transversely intersected has the enhanced cross-sectional configuration. A tiered transverse configuration is presented which facilitates electrical connection of the transfer metal to a metal level on a face of a semiconductor cube structure.