Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.