Abstract: Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described.

Abstract: Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.

Abstract: An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.

Abstract: A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

Abstract: In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written to a portion of the memory circuit. The majority voter circuit determines if the data bits are to be inverted prior to being written into the memory circuit portion.

Abstract: For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.

Abstract: A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

Abstract: A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.

Abstract: A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

Abstract: A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.

Abstract: A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.

Abstract: In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

Abstract: A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding scheme for searching the memory. Two or more cells in the memory may be consecutive bit positions of a word, and the driver may be synchronously operated to generate the different combinations of values.

Abstract: A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.

Abstract: A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.

Abstract: A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

Abstract: A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured dies. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.

Abstract: A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.