Abstract: An electronic device with a small outline no-lead package having a molded package structure and conductive leads with plated sidewalls exposed along opposite lateral sides of the package structure, a semiconductor die at least partially enclosed by the molded package structure, a first bond wire enclosed by the molded package structure and connected between a first one of the conductive leads and the semiconductor die, and a second bond wire having a first end and an unterminated second end exposed along a further side of the package structure.

Abstract: An example electronic device including a semiconductor die and a mold compound overlying the die, and the mold compound is chemically altered to attenuate electromagnetic radiation within a range of wavelengths or frequencies.

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Abstract: Disclosed examples include microelectronic devices, e.g. Integrated circuits. One example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (LDMOS) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. A superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. A drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.

Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.

Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.

Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.

Abstract: An apparatus includes an electrical device having a surface. The electrical device includes a first surface conductor spaced apart from a second surface conductor on the surface to provide circuit contacts to the device. A first standoff connector is bonded to the first surface conductor. The first standoff connector includes a leg having a proximal end bonded to the first surface conductor. The leg of the first standoff connector extends outwardly from the first surface conductor to a bend that is spaced apart from the surface of the electrical device. A second standoff connector is bonded to the second surface conductor. The second standoff connector includes a leg having a proximal end bonded to the second surface conductor. The leg of the second standoff connector extends outwardly from the second surface conductor to a bend that is spaced apart from the surface of the electrical device.

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.

Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.

Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.

Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Abstract: A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.