Patents by Inventor Steven Kummerl
Steven Kummerl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170196090Abstract: An apparatus includes an electrical device having a surface. The electrical device includes a first surface conductor spaced apart from a second surface conductor on the surface to provide circuit contacts to the device. A first standoff connector is bonded to the first surface conductor. The first standoff connector includes a leg having a proximal end bonded to the first surface conductor. The leg of the first standoff connector extends outwardly from the first surface conductor to a bend that is spaced apart from the surface of the electrical device. A second standoff connector is bonded to the second surface conductor. The second standoff connector includes a leg having a proximal end bonded to the second surface conductor. The leg of the second standoff connector extends outwardly from the second surface conductor to a bend that is spaced apart from the surface of the electrical device.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventor: Steven KUMMERL
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Publication number: 20170194233Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventors: Abram M. Castro, Steven Kummerl
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Publication number: 20160268023Abstract: A transfer mold compound mixture for use in a transfer mold device to encapsulate electronic components. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound.Type: ApplicationFiled: May 26, 2016Publication date: September 15, 2016Inventors: Steven Kummerl, Richard J. Saye
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Patent number: 9378882Abstract: Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a substrate. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound. The mixed mold compound is applied to the substrate by way of a transfer mold process, wherein the mixed mold compound encapsulates the electronic component.Type: GrantFiled: December 16, 2011Date of Patent: June 28, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Richard J. Saye
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Publication number: 20160163630Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.Type: ApplicationFiled: January 19, 2016Publication date: June 9, 2016Inventor: STEVEN KUMMERL
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Patent number: 9241405Abstract: A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded metal wires. A sealing material is added to sidewalls of a volume having the plurality of extruded metal wires within, with the first and second plattens as end plates to form a holding volume. The holding volume is filled with a filling material. The filling material is heated to a sufficient temperature to form a heat treated filled volume. After removing the sealing material, the heat treated filled volume is sawed into a plurality of slices having a predetermined thickness to form a plurality of interposer substrates having a plurality of feed-thru conducting features provided by the plurality of extruded metal wires.Type: GrantFiled: March 6, 2013Date of Patent: January 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Kummerl
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Publication number: 20130233609Abstract: A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded metal wires. A sealing material is added to sidewalls of a volume having the plurality of extruded metal wires within, with the first and second plattens as end plates to form a holding volume. The holding volume is filled with a filling material. The filling material is heated to a sufficient temperature to form a heat treated filled volume. After removing the sealing material, the heat treated filled volume is sawed into a plurality of slices having a predetermined thickness to form a plurality of interposer substrates having a plurality of feed-thru conducting features provided by the plurality of extruded metal wires.Type: ApplicationFiled: March 6, 2013Publication date: September 12, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: STEVEN KUMMERL
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Publication number: 20130154148Abstract: Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a substrate. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound. The mixed mold compound is applied to the substrate by way of a transfer mold process, wherein the mixed mold compound encapsulates the electronic component.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Richard J. Saye
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Publication number: 20120199951Abstract: An integrated circuit package that comprises a lead frame 105, an integrated circuit located on the lead frame and a shunt resistor coupled to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.Type: ApplicationFiled: March 5, 2012Publication date: August 9, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ubol Udompanyavit, Steven Kummerl
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Patent number: 8129228Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.Type: GrantFiled: October 25, 2010Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Ubol Udompanyavit, Sreenivasan K Koduri, Gerald W Steele, Jason M Cole, Steven Kummerl
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Publication number: 20110033985Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.Type: ApplicationFiled: October 25, 2010Publication date: February 10, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ubol Udompanyavit, Sreenivasan K. Koduri, Gerald W. Steele, Jason Marc Cole, Steven Kummerl
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Patent number: 7847391Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.Type: GrantFiled: July 1, 2008Date of Patent: December 7, 2010Assignee: Texas Instruments IncorporatedInventors: Ubol Udompanyavit, Sreenivasan K. Koduri, Gerald William Steele, Jason Marc Cole, Steven Kummerl
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Patent number: 7741704Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.Type: GrantFiled: October 18, 2007Date of Patent: June 22, 2010Assignees: Texas Instruments Incorporated, Texas Instruments Deutschland GmbHInventors: Bernhard Lange, Steven Kummerl
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Publication number: 20100001382Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.Type: ApplicationFiled: July 1, 2008Publication date: January 7, 2010Applicant: Texas Instruments IncorporatedInventors: Ubol Udompanyavit, Sreenivasan K. Koduri, Gerald William Steele, Jason Marc Cole, Steven Kummerl
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Publication number: 20080093715Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.Type: ApplicationFiled: October 18, 2007Publication date: April 24, 2008Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Bernhard Lange, Steven Kummerl
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Publication number: 20080094082Abstract: A semiconductor wafer adapted to wirelessly transfer data to a testing system. The wafer comprises a plurality of dies, each die adjacent another die and each die comprising an infrared transceiver. A first infrared transceiver transfers data to a second infrared transceiver by emitting a pattern of infrared light pulses representative of the data.Type: ApplicationFiled: December 18, 2007Publication date: April 24, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Kummerl
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Publication number: 20080020517Abstract: According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is disposed at least partially within the mold compound and is operable to facilitate transmission of a signal. The second lead frame is disposed at least partially within the compound, at least partially separated from the first lead frame, and is operable to facilitate a dissipation of thermal energy.Type: ApplicationFiled: July 31, 2007Publication date: January 24, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Bernhard Lange, Anthony Coyle
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Publication number: 20070259484Abstract: An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.Type: ApplicationFiled: July 9, 2007Publication date: November 8, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Anthony Coyle, Bernhard Lange
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Publication number: 20070181652Abstract: A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an ultrasonic bond capillary (102) and clamping the ribbon wire against an engagement surface (120) of the bond capillary via a clamping jaw (118) operably coupled to the bond capillary. The ribbon wire (104) is bonded to the workpiece (106) along a bonding surface (112) of the bond capillary (102) and penetrated, at least partially, between the bonding surface and the engagement surface (120) of the bond capillary by a cutting tool (124). The cutting tool (124) may comprise an elongate member (126) positioned between the bonding surface (112) and engagement surface (120), and may have a cutting blade (128) positioned at a distal end (130) thereof. The cutting tool (124) may further comprise a ring cutter (132), wherein the ribbon wire passes through a ring (134) having a cutting surface (138) defined about an inner diameter thereof.Type: ApplicationFiled: April 11, 2007Publication date: August 9, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Bernhard Lange, Steven Kummerl
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Publication number: 20060289971Abstract: A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar pad of a size matching the leadframe pad size, and contours (922), into which the leadframe members are inserted so that the first spreader pad surface touches the second leadframe pad surface across the pad size. A semiconductor chip (904) is mounted on the first leadframe pad surface. Encapsulation material (930), preferably molding compound, covers the chip, but leaves the second spreader surface uncovered.Type: ApplicationFiled: June 27, 2005Publication date: December 28, 2006Inventors: Bernhard Lange, Steven Kummerl