Patents by Inventor Steven Lemke

Steven Lemke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11270763
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 8, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11270771
    Abstract: A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate. First lines each electrically connect together the first gates in one of the memory cell rows, second lines each electrically connect together the source regions in one of the memory cell rows, and third lines each electrically connect together the drain regions in one of the memory cell columns. The synapses are configured to receive a first plurality of inputs as electrical voltages on the first lines or on the second lines, and to provide a first plurality of outputs as electrical currents on the third lines.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 8, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20210407588
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11183506
    Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 23, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jinho Kim, Xian Liu, Feng Zhou, Parviz Ghazavi, Steven Lemke, Nhan Do
  • Publication number: 20210358551
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.
    Type: Application
    Filed: October 28, 2020
    Publication date: November 18, 2021
    Inventors: HIEU VAN TRAN, STANLEY HONG, STEPHEN TRINH, THUAN VU, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
  • Patent number: 11158374
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 26, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • Publication number: 20210305264
    Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.
    Type: Application
    Filed: October 13, 2020
    Publication date: September 30, 2021
    Inventors: Feng Zhou, Xian Liu, Steven Lemke, Hieu Van Tran, Nhan Do
  • Publication number: 20210295907
    Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.
    Type: Application
    Filed: September 17, 2020
    Publication date: September 23, 2021
    Inventors: HIEU VAN TRAN, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
  • Publication number: 20210264983
    Abstract: Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.
    Type: Application
    Filed: August 4, 2020
    Publication date: August 26, 2021
    Inventors: Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'Mani, Thuan Vu, Nhan Do, Vipin Tiwari
  • Publication number: 20210209457
    Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 8, 2021
    Inventors: Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
  • Publication number: 20210209458
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 8, 2021
    Inventors: Hieu Van Tran, STEVEN LEMKE, NHAN DO, MARK REITEN
  • Publication number: 20210209456
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 8, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20210142156
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 13, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20210098477
    Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
  • Publication number: 20210090654
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 25, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • Publication number: 20210089875
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 25, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20210019608
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Publication number: 20210020255
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Publication number: 20200395370
    Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 17, 2020
    Applicant: Silicon Storage Technology,Inc.
    Inventors: Jinho Kim, XIAN LIU, FENG ZHOU, PARVIZ GHAZAVI, STEVEN LEMKE, NHAN DO
  • Publication number: 20200350015
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: HIEU VAN TRAN, STEVEN LEMKE, NHAN DO, VIPIN TIWARI, MARK REITEN