Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

Abstract: A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate. First lines each electrically connect together the first gates in one of the memory cell rows, second lines each electrically connect together the source regions in one of the memory cell rows, and third lines each electrically connect together the drain regions in one of the memory cell columns. The synapses are configured to receive a first plurality of inputs as electrical voltages on the first lines or on the second lines, and to provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

Abstract: A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: Numerous embodiments are disclosed for providing temperature compensation and leakage compensation for an analog neuromorphic memory system used in a deep learning neural network. The embodiments for providing temperature compensation implement discreet or continuous adaptive slope compensation and renormalization for devices, reference memory cells, or selected memory cells in the memory system. The embodiments for providing leakage compensation within a memory cell in the memory system implement adaptive erase gate coupling or the application of a negative bias on a control gate terminal, a negative bias on a word line terminal, or a bias on a source line terminal.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

Abstract: A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stripping away the layer of amorphous silicon, wherein some of the amorphous silicon remains in the upper surface of the first layer of conductive material, forming a layer of transition metal oxide material on the upper surface of the first layer of conductive material, and forming a second layer of conductive material on the layer of transition metal oxide material. The method smoothes the upper surface of the bottom electrode, and also provides an bottom electrode upper surface with stable material that is hard to oxidize.

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

Abstract: Embodiments of this invention provide for a portable computer that determines whether an accessory device is actively connected to it. In one embodiment, the portable computer may include a signal line accessible through an output of the portable computing device. The signal line may be connected to a communication device such as a communication cradle. The portable computer may detect a signal on the signal line to determine whether the communication device is actively connected to the portable computer. If the communication device is actively connected, the portable computer suspends implementation of a time-out feature that would otherwise reduce power consumption of the portable computer.

Abstract: Techniques to create a portable wireless network are described. A mobile computing device may comprise a first transceiver to communicate with a fixed wireless device, and a second transceiver to communicate with multiple wireless devices. The mobile computing device may also include a network access management module to manage communications between each wireless device and the fixed wireless device. Other embodiments are described and claimed.

Abstract: A method of indexing information stored on a portable electronic device. The method includes receiving an association signal by the portable electronic device the association signal providing an indication of adjacent resources, accessing a database including a table storing relationships between data stored on the portable electronic device and the association signal, and indexing the data based on the relationships accessed in the database.

Abstract: A system and method for crediting an account of a network access node includes receiving a data signal at a network access node, forwarding the data signal wirelessly to a network user node, and providing account crediting information to an accounting system. The account crediting information represents a credit to be recorded for an account associated with the network access node.

Abstract: A method and system of providing compatibility between a software application and an electronic device are disclosed. An exemplary method includes providing an electronic device having a processor and a memory, the processor running an operating system. The method also includes providing access to a software application configured to run on the process of the electronic device. Further, the method includes checking operating system compatibility information. The operating system compatibility information is included in the software application.