Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.

Abstract: SOC and other chip designs increasingly feature IP cores, and many copies of the same core may be present in a single chip. Using wrapped cores, it is possible to determine which cores are defective on a chip during test. Multiple instances of identical cores may be tested in parallel to easily determine which cores are failing. The cores compare a signature generated during test of the core against an expected signature, having a pass/fail bit as a result. The pass/fail bits may be multiplexed at an output pin where output pins are at a premium relative to the number of core instances or the pass/fail bit stored in a register to be later serially-unloaded from the chip. The disclosed embodiments provide for masking circuitry, as well as both identical and different core instances to be run serially and in parallel.

Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

Abstract: A method of masking scan channels in a semiconductor chip includes storing, in first and second memories of a first mask logic, first and second channel mask enable decodes for first and second masks that mask first and second scan channels of a circuit under test; receiving at least three channel enable signals on three respective enable pins to produce a channel mask enable encode; comparing the channel mask enable encode to the stored first and second enable decodes; and masking the first or second scan channel when the channel mask enable encode respectively matches the first or second channel mask enable decode.

Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches data source. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. A related latches table may be created by tracing from a target latch.

Abstract: A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

Abstract: A method and apparatus are provided for isolating a defect in a scan chain comprising a plurality of components of an integrated circuit. A plurality of injection points may be positioned along the scan chain. Each injection point may be configured to introduce binary test data. A plurality of bypass structures may each be configured to selectively direct a flow of the binary test data to generate a plurality of partitioned scan paths. Test logic may be configured to execute a plurality of tests using the plurality of partitioned scan paths and to combine results of the plurality of tests to isolate a faulty component of the plurality of components.

Abstract: A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

Abstract: A method and apparatus are provided for isolating a defect in a scan chain comprising a plurality of components of an integrated circuit. A plurality of injection points may be positioned along the scan chain. Each injection point may be configured to introduce binary test data. A plurality of bypass structures may each be configured to selectively direct a flow of the binary test data to generate a plurality of partitioned scan paths. Test logic may be configured to execute a plurality of tests using the plurality of partitioned scan paths and to combine results of the plurality of tests to isolate a faulty component of the plurality of components.

Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

Abstract: A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output. The first mask logic includes at least three enable pins that receive respective enable signals. The three enable signals produce a channel mask enable encode. The first mask logic includes a first memory that stores a first channel mask enable decode for the first mask and a second memory that stores a second channel mask enable decode for the second mask. The first mask logic includes a first comparator and a second comparator. The first and second comparator compare the respective channel mask enable decodes to the channel mask enable encode. The comparators signal respective masks to mask the respective scan channel when the respective channel mask enable decode matches the channel mask enable encode.

Abstract: A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.

Abstract: A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.

Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.

Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.

Abstract: First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.

Abstract: A method of creating a scan pattern test file for testing hierarchal test blocks (HTBs) of scan channels on a semiconductor chip is described. The method includes determining a maximum number of channel mask enable encodes on the semiconductor chip. A maximum number of channel mask enable encodes used for the first HTB and the second HTB are determined. A plurality of test patterns used to test the first and the second HTB into one or more mask sets dependent on the number of masks each test pattern needs are sorted. The test patterns of the mask sets of the first and second HTB to be performed in a same test pattern are combined. The number of masks per scan cycle of the combined mask sets is no more than the maximum number of channel mask enable encodes on the semiconductor chip and there is no scan slice overlap.