Patents by Inventor Steven M. Douskey

Steven M. Douskey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9110135
    Abstract: First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Mary P. Kusko, Cedric Lichtenau
  • Patent number: 9103879
    Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 9069041
    Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20150168490
    Abstract: A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
  • Publication number: 20150168491
    Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches data source. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. A related latches table may be created by tracing from a target latch.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
  • Patent number: 9032256
    Abstract: Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Dennis M. Rickert
  • Publication number: 20150113348
    Abstract: A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Mary P. Kusko, Cédric Lichtenau
  • Patent number: 9003244
    Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20150089311
    Abstract: A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Mary P. Kusko, Cedric Lichtenau
  • Publication number: 20150089312
    Abstract: A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel.
    Type: Application
    Filed: December 17, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Mary P. Kusko, Cedric Lichtenau
  • Publication number: 20150039957
    Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 8898530
    Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20140331097
    Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20140325298
    Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.
    Type: Application
    Filed: July 11, 2014
    Publication date: October 30, 2014
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 8868975
    Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ralph E. Bellofatto, Steven M. Douskey, Rudolf A. Haring, Moyra K. McManus, Martin Ohmacht, Dietmar Schmunkamp, Krishnan Sugavanam, Bryan J. Weatherford
  • Patent number: 8856720
    Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20140298124
    Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ronald E. Fuhs
  • Publication number: 20140201575
    Abstract: Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Dennis M. Rickert
  • Publication number: 20140189612
    Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.
    Type: Application
    Filed: January 3, 2013
    Publication date: July 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 8762803
    Abstract: A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer