Abstract: A method and system for built-in self-testing architecture, including: a logic built-in self-test (LBIST) controller in operable communication with a pseudo-random pattern generator; a multiple input signature register in operable communication with a plurality of scan channels; and circuitry in operable communication with the pseudo-random pattern generator and the multiple input signature register, wherein the circuitry includes a channel skip function which allows selection of any combination of scan channels to skip while scanning.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: An electronics systems having variable interconnections among major components is tested by dynamically identifying the locations and types of all system components at the time the test is to be performed, for building a global model describing the interconnections among these components. Specific tests appropriate for this model are then dynamically generated and executed. Data on the components themselves identifies them. The tests employ boundary-scanning techniques to locate failing drivers, receivers, and bidirectional driver/receivers, as well as open and shorted interconnections.

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing an oscillator input signal to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) are providing in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.