Patents by Inventor Steven M. Shank

Steven M. Shank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203478
    Abstract: The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: STEVEN M. SHANK, MARK David LEVY, BRUCE W. PORTH
  • Publication number: 20200176304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Siva P. ADUSUMILLI, Steven M. SHANK, John J. ELLIS-MONAGHAN, Anthony K. STAMPER
  • Publication number: 20200141810
    Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Vibhor Jain, Anthony K. Stamper, John J. Pekarik, Steven M. Shank
  • Patent number: 10642125
    Abstract: Structures providing optical beam steering and methods of fabricating such structures. A first grating coupler has a first plurality of grating structures spaced with a first pitch along a first axis. A second grating coupler has a second plurality of grating structures spaced with a second pitch along a second axis. An optical switch is coupled to the first grating coupler and to the second grating coupler. The optical switch is configured to select between the first grating coupler and the second grating coupler for optical signal routing. The second axis of the second grating coupler is aligned nonparallel to the first axis of the first grating coupler.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik
  • Patent number: 10629482
    Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10622496
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Publication number: 20200075781
    Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Solomon Assefa, Tymon Barwicz, William M. Green, Marwan H. Khater, Jessie C. Rosenberg, Steven M. Shank
  • Publication number: 20200075783
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Patent number: 10580893
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan
  • Patent number: 10573554
    Abstract: A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Publication number: 20200058807
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Patent number: 10566235
    Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 10546962
    Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Tymon Barwicz, William M. Green, Marwan H. Khater, Jessie C. Rosenberg, Steven M. Shank
  • Patent number: 10535787
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Publication number: 20200013855
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Anthony K. STAMPER, Steven M. SHANK, John J. ELLIS-MONAGHAN, Siva P. ADUSUMILLI
  • Patent number: 10509244
    Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan, Vibhor Jain, John J. Pekarik
  • Publication number: 20190348550
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Patent number: 10466514
    Abstract: Structures for an electro-optic modulator and methods of fabricating such structures. A first plurality of cavities are formed in a bulk semiconductor substrate. A passive waveguide arm includes a first core arranged over the first plurality of cavities. The passive waveguide arm has an input port and an output port that is spaced lengthwise from the input port. An epitaxial semiconductor layer is arranged over the bulk semiconductor substrate, and includes a second plurality of cavities. An active waveguide arm includes a second core that is arranged over the second plurality of cavities. The second core of the active waveguide arm is coupled with the input port of the first core of the passive waveguide arm, and the second core of the active waveguide arm is also coupled with the output port of the first core of the passive waveguide arm.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Siva P. Adusumilli
  • Patent number: 10461152
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, Siva P. Adusumilli
  • Patent number: 10446435
    Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Michel Abou-Khalil