Patents by Inventor Steven M. Shank

Steven M. Shank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085624
    Abstract: Structures including an electro-absorption modulator and methods of forming such structures. The structure comprises a waveguide core including a first tapered section, a second tapered section, and a longitudinal axis. The first tapered section and the second tapered section are aligned along the longitudinal axis. The structure further comprises a first waveguide taper overlapping the first tapered section of the waveguide core, a second waveguide taper overlapping the second tapered section of the waveguide core, and a multiple-layer structure on the waveguide core between the first waveguide taper and the second waveguide taper.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Yusheng Bian, Steven M. Shank, Judson Holt, Michal Rakowski, Bartlomiej Jan Pawlak
  • Publication number: 20240088157
    Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Michel Abou-Khalil, Steven M. Shank, Sarah McTaggart, Aaron Vallett, Rajendran Krishnasamy, Megan Lydon-Nuhfer
  • Publication number: 20240045156
    Abstract: A structure includes a dielectric waveguide, and at least one grating coupler adjacent the dielectric waveguide. Each grating coupler includes a set of parallel optofluidic grating channels oriented orthogonally to the dielectric waveguide. The structure may also include a radiation source operatively coupled to the dielectric waveguide, and an optical receiver such as a photosensor adjacent the grating coupler(s). The structure may be used as part of an optofluidic sensor system for, for example, biochemical applications.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: Yusheng Bian, Vibhor Jain, Steven M. Shank
  • Publication number: 20240045140
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Inventors: Yusheng BIAN, Ajey Poovannummoottil JACOB, Steven M. SHANK
  • Patent number: 11880065
    Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes an edge coupler having a longitudinal axis, a first ring resonator, and a second ring resonator. The first ring resonator has a first center point that is spaced from the longitudinal axis of the edge coupler by a first perpendicular distance. The second ring resonator has a second center point that is spaced from the longitudinal axis of the edge coupler by a second perpendicular distance.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 23, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Yusheng Bian, Steven M. Shank, Takako Hirokawa
  • Patent number: 11862511
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: January 2, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Steven M. Shank, Siva P. Adusumilli, Alvin Joseph
  • Patent number: 11848192
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: December 19, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Steven M. Shank, John J. Pekarik
  • Patent number: 11848324
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: December 19, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ephrem G. Gebreselasie, Steven M. Shank, Alain F. Loiseau, Robert J. Gauthier, Jr., Michel J. Abou-Khalil, Ahmed Y. Ginawi
  • Publication number: 20230402453
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 14, 2023
    Inventors: Vibhor JAIN, John J. ELLIS-MONAGHAN, Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK
  • Publication number: 20230378183
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Anthony K. STAMPER, Uzma RANA, Siva P. ADUSUMILLI, Steven M. SHANK
  • Patent number: 11822122
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: November 21, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Steven M. Shank
  • Patent number: 11823948
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: November 21, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Uzma Rana, Anthony K. Stamper, Steven M. Shank, Brett T. Cucci
  • Patent number: 11817479
    Abstract: A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: November 14, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Uzma B. Rana, Steven M. Shank, Anthony K. Stamper
  • Patent number: 11803009
    Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Yusheng Bian, Steven M. Shank, Judson Holt
  • Patent number: 11791334
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: October 17, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, John J. Ellis-Monaghan, Anthony K. Stamper, Steven M. Shank, John J. Pekarik
  • Publication number: 20230317869
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Rajendran Krishnasamy, John J. Ellis-Monaghan, Siva P. Adusumilli, Ramsey Hazbun, Steven M. Shank
  • Publication number: 20230317776
    Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Michel Abou-Khalil, Steven M. Shank, Aaron Vallett, Sarah McTaggart, Rajendran Krishnasamy
  • Publication number: 20230299132
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Vibhor JAIN, Anthony K. STAMPER, John J. ELLIS-MONAGHAN, Steven M. SHANK, Rajendran KRISHNASAMY
  • Patent number: 11764225
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 19, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Uzma Rana, Siva P. Adusumilli, Steven M. Shank
  • Patent number: 11764060
    Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: September 19, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Michel J. Abou-Khalil, Steven M. Shank, Alvin J. Joseph, Michael J. Zierak