Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The isolation structure includes: a polycrystalline isolation layer under the active device, a trench isolation adjacent the active device, and a porous semiconductor layer between the trench isolation and the bulk semiconductor substrate.

Abstract: A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant.

Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.

Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

Abstract: Structures for a polarization rotator and methods of fabricating a structure for a polarization rotator. The structure includes a substrate, a first waveguide core over the substrate, and a second waveguide core over the substrate. The second waveguide core is positioned proximate to the section of the first waveguide core. The second waveguide core is comprised of a material having a refractive index that is reversibly variable in response to a stimulus.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance.