Patents by Inventor Steven T. Mayer

Steven T. Mayer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090280243
    Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 12, 2009
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
  • Publication number: 20090277867
    Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
    Type: Application
    Filed: November 20, 2006
    Publication date: November 12, 2009
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
  • Publication number: 20090266707
    Abstract: Pad-assisted electropolishing of the substrate is conducted by performing anodic dissolution of metal at a first portion of the substrate and simultaneously mechanically buffing a second portion of the substrate with a buffing pad. Anodic dissolution includes forming a thin liquid layer of electropolishing liquid between the anodic substrate and a cathodic electropolishing head. The location of electrical contacts between the substrate and power supply allow peripheral edge regions of the substrate to be mechanically buffed with the pad. Preferably, a substrate is further planararized using an isotropic material-removal technique. An apparatus includes an electropolishing head that is movable to a position proximate to a first portion of a substrate to form a thin gap, and a buffing pad that mechanically buffs a second portion of the substrate using minimal pressure.
    Type: Application
    Filed: August 6, 2007
    Publication date: October 29, 2009
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Julia Svirchevski, John Stephen Drewery
  • Patent number: 7605082
    Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: October 20, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
  • Patent number: 7560016
    Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: July 14, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John Stephen Drewery
  • Patent number: 7531079
    Abstract: The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: May 12, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John S. Drewery
  • Patent number: 7531463
    Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: May 12, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Daniel A. Koos, Steven T. Mayer, Heung L. Park, Timothy Patrick Cleary, Thomas Mountsier
  • Patent number: 7449098
    Abstract: A disclosed form of mechanically assisted electroplating leads to a flat, thin, overburden. In one example, an accelerator is deposited on a copper surface and mechanically removed in a simplified CMP-like apparatus. The wafer is then plated in an electrolyte containing little or no accelerating additives.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: November 11, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan D. Reid, Mark L. Rea, Ismail T. Emesh, Henner W. Meinhold, John S. Drewery
  • Patent number: 7449099
    Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: November 11, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John Stephen Drewery
  • Patent number: 7405163
    Abstract: An accelerator solution is globally applied to a workpiece to form an accelerator film, and then a portion of the accelerator film is selectively removed from the workpiece to form an acceleration region having a higher concentration of accelerator. The higher concentration of accelerator causes metal to deposit at a faster rate in the acceleration region than in a non-accelerated region for the duration of metal deposition. To make a metal feature, a resist layer is applied to a workpiece surface and patterned to form a recessed region and a field region. Then, a metal seed layer is deposited on the workpiece surface. An accelerator solution is applied so that an accelerator film forms on the metal seed layer. A portion of the accelerator film is selectively removed from the field region, leaving another portion of the accelerator film in the recessed region.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: July 29, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: John Stephen Drewery, Steven T. Mayer
  • Patent number: 7338908
    Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: March 4, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Daniel A. Koos, Steven T. Mayer, Heung L. Park, Timothy Patrick Cleary, Thomas Mountsier
  • Patent number: 7211175
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 7189647
    Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: March 13, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Evan E. Patton, Theodore Cacouris, Eliot Broadbent, Steven T. Mayer
  • Patent number: 7097410
    Abstract: The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: August 29, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Steven T. Mayer, Seshasayee Varadarajan, David C. Smith, Evan E. Patton, Dinesh S. Kalakkad, Gary Lind, Richard S. Hill
  • Patent number: 7070686
    Abstract: In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: July 4, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Robert J. Contolini, Andrew J. McCutcheon, Steven T. Mayer
  • Patent number: 6967174
    Abstract: A wafer chuck includes alignment members that allows a semiconductor wafer to be properly aligned on the chuck without using a separate alignment stage. The alignment members may be cams, for example, attached to arms of the wafer chuck. These members may assume an alignment position when a robot arm places the wafer on the chuck. In this position, they guide the wafer into a proper alignment position with respect to the chuck. During rotation at a particular rotational speed, the alignment members move away from the wafer to allow liquid etchant to flow over the entire edge region of the wafer. At still higher rotational speeds, the wafer is clamped into position to prevent it from flying off the chuck. A clamping cam or other device (such as the alignment member itself) may provide the clamping.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 22, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Steve Taatjes, Andy McCutcheon, Jim Schall, Jingbin Feng
  • Patent number: 6964792
    Abstract: The present invention provides apparatus and methods for controlling flow dynamics of a plating fluid during a plating process. The invention achieves this fluid control through use of a diffuser membrane. Plating fluid is pumped through the membrane; the design and characteristics of the membrane provide a uniform flow pattern to the plating fluid exiting the membrane. Thus a work piece, upon which a metal or other conductive material is to be deposited, is exposed to a uniform flow of plating fluid.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: November 15, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, R. Marshall Stowell, Evan E. Patton, Seshasayee Varadarajan
  • Patent number: 6946065
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 20, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Patent number: 6919010
    Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. The current of a plating cell is provided from an azimuthally asymmetric anode, which is rotated with respect to the work piece (i.e., either or both of the work piece and the anode may be rotating). The azimuthal asymmetry provides a time-of-exposure correction to the current distribution reaching the work piece, whereby peripheral regions of the work piece see less current than central regions over the period of rotation. In some embodiments, the total current is distributed among a plurality of anodes in the plating cell in order to tailor the current distribution in the plating electrolyte over time. Focusing elements may be used to create “virtual anodes” in proximity to the plating surface of the work piece to further control the current distribution in the electrolyte during plating.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: July 19, 2005
    Assignee: Novellus Systems, Inc.
    Inventor: Steven T. Mayer
  • Patent number: 6890416
    Abstract: An electroplating apparatus prevents anode-mediated degradation of electrolyte additives by creating a mechanism for maintaining separate anolyte and catholyte and preventing mixing thereof within a plating chamber. The separation is accomplished by interposing a porous chemical transport barrier between the anode and cathode. The transport barrier limits the chemical transport (via diffusion and/or convection) of all species but allows migration of ionic species (and hence passage of current) during application of sufficiently large electric fields within electrolyte.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: May 10, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Evan E. Patton, Robert L. Jackson, Jonathan D. Reid