Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

Abstract: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Abstract: Some embodiments of the invention provide a via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. At least some of the configurable circuits are via programmable (“VP”) configured circuits. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several bit lines, where at least one the bit line provides a configuration value to at least one configurable circuit. In some embodiments, at least some bit lines traverse along more than one column or row in the circuit arrangement.

Abstract: Some embodiments of the invention provide configurable via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several direct offset connections, where each particular direct offset connection connects two configurable circuits that are neither in the same column nor in the same row in the circuit arrangement. In some embodiments, at least some direct offset connections connect pairs of circuits that are separated in the circuit arrangement by more than one row and at least one column, or by more than one column and at least one row. At least some of the configurable circuits are via programmable (“VP”) configured circuits.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets.

Abstract: Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a two-input multiplexer. The second IMUX is also configured as a two-input multiplexer. The LUT is also configured as a third two-input multiplexer. An output of the first IMUX is connected to the first input of the LUT, an output of the second IMUX is connected to the second input of the LUT. A third input of the LUT accepts a selection bit.

Abstract: Some embodiments provide a method of performing circuit synthesis that receives a design that has a function with several inputs. The method identifies a set of early arriving inputs of the function and performs a function decomposition on the function based on one of the early arriving inputs. In some embodiments, the method estimates the number of circuits a signal has to travel through to reach each input of the function and selects a set of inputs with signals that travel through fewer numbers of circuits compared to signals of inputs that are not selected. In some embodiments in which the design has more than a particular number of inputs, the method recursively identifies early arriving signals and performs function decomposition until function decomposition results in a set of functions all of which with fewer than the particular number of inputs. In some embodiments, the function decomposition is Shannon decomposition.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

Abstract: Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. In some embodiments a method uses at least a subset of the configurable logic circuits and a first subset of the configurable routing circuits to implement a user design circuit on the configurable IC. The method uses a second subset of the configurable routing circuits to pass signals to the network.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Abstract: Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the traced buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays.

Abstract: Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Abstract: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. Each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable routing interconnect circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any routing circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular routing circuit in any interior tile and any circuit that provides an input of the particular routing circuit.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set. The IC also has a second set of input terminals for carrying a set of input signals, where at least several of the second set of input terminals overlap at least a plurality of the first set of input terminals. The IC further has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set. The interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.

Abstract: Some embodiments provide an IC with a configurable node array that has (1) two similar nodes within the interior of the array, and (2) two different connection schemes. The first connection scheme specifies a set of connections between the first node and a set of nodes in the array, while the second connection scheme specifies a second set of connections between the second node and a set of nodes in the array. The two nodes cannot connect to any nodes on the boundary of the array with any connection that is specified in any connection scheme.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets.

Abstract: Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one period during the operation of the IC, the second network receives addresses for a several UDS circuits in a random access manner. In some embodiments, the second network is a debug network for reading randomly state values stored by the addressed UDS circuits during the user-design operation of the IC.