Patents by Inventor Steven Teig

Steven Teig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7545167
    Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurably routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: June 9, 2009
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Herman Schmit, Jason Redgrave, Vikas Chandra
  • Patent number: 7543251
    Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: June 2, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Asmus Hetzel
  • Patent number: 7535252
    Abstract: Some embodiments provide a method of operating a configurable circuit. The method performs a first operation by the configurable circuit based on a first configuration data set. When a user-design signal has a value from a set of values, the method performs a second operation based on a second configuration data set, after the first operation. When the user-design signal does not have a value from said set of values, the method performs a third operation based on a third configuration data set, after the first operation. Some embodiments provide a reconfigurable IC that includes a set of reconfigurable circuits and sets of associated configuration storage elements that store configuration data sets. At least one reconfigurable circuit receives a first sub-set of its configuration data when a user-design signal has a first value and receives a second sub-set of its configuration data when the user-design signal has a second value.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: May 19, 2009
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Andrew Caldwell, Jason Redgrave
  • Patent number: 7532032
    Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can configurably perform a set of functions. The configurable interconnect circuits can configurably couple the logic circuits. At least several of the configurable circuits can be reconfigured faster than the first rate.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 12, 2009
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Patent number: 7528627
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 5, 2009
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Brad Hutchings, Herman Schmit, Steven Teig
  • Patent number: 7530044
    Abstract: Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies several integrated circuits (“IC's”) for performing the set of operations. The method packages several of identified IC's into a single IC package. The several identified IC's includes at least one configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: May 5, 2009
    Assignee: Tabula, Inc.
    Inventor: Steven Teig
  • Patent number: 7529992
    Abstract: An integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data and error correction data, and error correction circuitry for receiving the configuration data, correcting a particular error in the received configuration data when the particular error exists in the configuration data, and outputting the configuration data without the particular error. The IC further includes a configurable circuit (e.g., a configurable logic circuit or a configurable interconnect circuit) that receives the error-corrected configuration data from the error correction circuitry, and circuitry to write the corrected configuration data and error data back into the configuration memory.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: May 5, 2009
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Jason Redgrave, Timothy Horel
  • Patent number: 7530033
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 5, 2009
    Assignee: Tabula, Inc.
    Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
  • Patent number: 7525344
    Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
    Type: Grant
    Filed: May 27, 2007
    Date of Patent: April 28, 2009
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Herman Schmit, Jason Redgrave
  • Patent number: 7525342
    Abstract: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: April 28, 2009
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Herman Schmit, Jason Redgrave
  • Publication number: 20090106710
    Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.
    Type: Application
    Filed: October 25, 2008
    Publication date: April 23, 2009
    Inventors: Steven Teig, Asmus Hetzel
  • Patent number: 7521958
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: April 21, 2009
    Assignee: Tabula, Inc.
    Inventors: Brad Hutchings, Herman Schmit, Steven Teig
  • Patent number: 7521959
    Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
    Type: Grant
    Filed: May 27, 2007
    Date of Patent: April 21, 2009
    Assignee: Tabula, Inc.
    Inventor: Steven Teig
  • Patent number: 7518402
    Abstract: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: April 14, 2009
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Steven Teig, Brad Hutchings, Randy Renfu Huang, Jason Redgrave
  • Patent number: 7512850
    Abstract: Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: March 31, 2009
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Brad Hutchings, Herman Schmit, Steven Teig, Tom Kronmiller
  • Patent number: 7506295
    Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Steven Teig
  • Patent number: 7504858
    Abstract: Some aspects of the present invention involve connections in a configurable IC. Some embodiments provide a configurable integrated circuit with a first array of tiles. The first array of tiles has columns and rows of tiles. The IC has a first tile within the first array of tiles. The first tile has a set of outputs. The IC has a second tile in the array of tiles. The second tile has a set of inputs. The IC has a non-neighboring offset connection (NNOC) from an output of the first tile to an input of the second tile. The second tile is offset from the first tile by at least one row and at least two columns or by at least two rows and at least one column.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: March 17, 2009
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Steven Teig, Brad Hutchings
  • Publication number: 20090058461
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Patent number: 7496879
    Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations concurrently to different operational cycles and different configurable circuits. In some embodiments, the method concurrently optimizes the assignment of the operations to different operation cycles and different configurable circuits. In some embodiments, the optimization includes moving the operations between different operational cycles and different configurable circuits in order to identify an assignment of the operations that satisfies a set of optimization criteria.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: February 24, 2009
    Assignee: Tabula, Inc.
    Inventors: Andre Rohe, Steven Teig
  • Patent number: 7493581
    Abstract: Some embodiments provide an analytical placement method that considers diagonal wiring. This method formulates an objective function that accounts for the use of diagonal wiring during routing. Some embodiments use horizontal, vertical, and ±45° diagonal lines. For such a wiring model, some embodiments use the following objective function: Function = ? n ? ? p ? ( n ) ? b i , j ? ( 1 2 ? ( ? + ( x i - x j ) 2 + ? + ( y i - y j ) 2 ) + ( 1 - 1 2 ) ? ? + ( x i - x j ) 2 + ( y i - y j ) 2 - 2 ? ( x i - x j ) 2 ? ( y i - y j ) 2 ? + ( x i - x j ) 2 ? ( y i - y j ) 2 ) In this equation, n represents a net, p(n) represents a unique pair of pins i and j of the net n, x and y represent the x-, and y-coordinates of a particular pin, and bi,j represents a weighting factor that biases the function based on the desired closeness of pins i and j.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: February 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Siegel, Steven Teig, Hussein Etawil