Abstract: A gate-to-source voltage (Vgs) replication circuit includes a diode-connected NMOS transistor coupled to a current source to draw a drain-to-source current therethrough. The generated Vgs is imposed across a source-to-gate junction of a PMOS transistor. A second PMOS transistor is coupled in series with the first PMOS transistor such that the source-to-gate voltage (Vsg) of the second PMOS transistor replicates the Vgs of the NMOS circuit. The second PMOS transistor is coupled as a source follower to bias other NMOS transistors.

Abstract: A gain-step transconductor circuit operates with multiple gain values. The gain can be stepped from one gain value to another by selecting a different signal path between an input node and an output amplifier. The output amplifier may operate as a common source amplifier or a common gate amplifier.

Abstract: A low noise amplifier (LNA) is discussed. In implementations, a LNA may include a feedback section coupled to a transistor. The feedback section may have a resistive portion including a buffer and a resistor. A capacitor may be connected in parallel with the resistor. In additional implementations, an integrated circuit may include a second transistor connected to the drain of the first transistor. A feedback section may be coupled across the first and second transistors. The feedback section may include a buffer, a resistor and a capacitor connected in series, so that the terminal of the buffer is connected to the drain of the second transistor while the terminal of the resistor is connected to a source on the first transistor.

Abstract: A gain-step transconductor circuit operates with multiple gain values. The gain can be stepped from one gain value to another by selecting a different signal path between an input node and an output amplifier. The output amplifier may operate as a common source amplifier or a common gate amplifier.

Abstract: Embodiments related to resistive feedback amplifiers are presented herein.

Abstract: In some embodiments, an apparatus includes an amplifier circuit and a bias circuit coupled to the amplifier. The amplifier circuit includes an input port and an output port, an input port circuit element coupled to the input port, an output port circuit element coupled to the output port, and an internal signal path to couple the input port circuit element to the output port circuit element. The output port is coupled to the input port, the bias circuit, and the internal signal path.

Abstract: An apparatus reducing non-linearity in an output signal presented at an output locus of an amplifier device having an output unit coupled with the output locus, the output unit having at least one first operating characteristic contributing to the non-linearity, includes a compensating unit coupled with the output locus. The compensating unit has at least one second operating characteristic cooperating with the at least one first operating characteristic to effect the reducing.

Abstract: An apparatus and a system, as well as a method and an article, may include detecting an indication of an amplifier output signal amplitude and responsively adjusting the amplifier input signal phase to reduce a change in the phase of the output signal.

Abstract: A biased transistor circuit utilizes a transistor that exhibits a change in threshold voltage as the drain-to-source voltage changes due to power supply voltage changes. A bias circuit senses the power supply voltage changes and modifies a gate bias voltage on the transistor to maintain a substantially constant drain bias current in the transistor.

Abstract: An apparatus includes an input port, an output port, a resistor, and a current amplifier. The current amplifier includes an input circuit and an output circuit. The resistor is coupled to the input port. The input circuit is coupled to the resistor and the output circuit. The output circuit is coupled to the output port, the input circuit and the output circuit. The input circuit and output circuit have substantially identical topologies. A method includes receiving an input voltage signal, converting the input voltage signal to a current signal, and processing the current signal to form a feedback signal and an output current signal that is a substantially linear representation of the input voltage signal.

Abstract: A bias circuit is provided to present a controlled impedance to an input of an RF amplifier to improve linearity of the RF amplifier. The bias circuit may control the impedance such that a low impedance is presented to the input of the amplifier at low frequencies and a high impedance is presented to the input of the amplifier at high frequencies.

Abstract: A radio frequency (RF) power amplification system uses multiple DC power sources to achieve efficient operation. In at least one embodiment, linear operation is maintained by appropriately selecting a reference voltage at which a secondary power source is activated.

Abstract: An operating voltage applied to a transmitter's power amplifier in a mobile wireless transceiver is dynamically controlled so as to improve the efficiency of the transmitter at all output power levels. In one embodiment, the bias current levels within the transmitter are also varied to optimize the efficiency of the transmitter at all output power levels. In a preferred embodiment, a highly efficient switching regulator is controlled by a control circuit to adjust the operating voltage and/or bias current for the power amplifier in the transmitter. The control circuit has as its input any of a variety of signals which reflect the actual output power of the transmitter, the desired output power, or the output voltage swing of the transmitter.

Abstract: An operating voltage applied to a transmitter's power amplifier in a mobile wireless transceiver is dynamically controlled so as to improve the efficiency of the transmitter at all output power levels. In one embodiment, the bias current levels within the transmitter are also varied to optimize the efficiency of the transmitter at all output power levels. In a preferred embodiment, a highly efficient switching regulator is controlled by a control circuit to adjust the operating voltage and/or bias current for the power amplifier in the transmitter. The control circuit has as its input any of a variety of signals which reflect the actual output power of the transmitter, the desired output power, or the output voltage swing of the transmitter.

Abstract: An RF power amplifier with variable bias current is disclosed. The RF amplifier includes a peak detector that detects the peak level of the amplifier input signal. The peak detector generates an output signal in response to the peak level of the amplifier input signal. A bias voltage level setting circuit coupled to the peak detector receives the peak detector output signal and generates a bias voltage in response to the peak detector output signal. An amplifier circuit coupled to the bias voltage level setting circuit receives the bias voltage and the amplifier input signal, and generates an output signal in response to the bias voltage and the amplifier input signal. The disclosed RF amplifier allows amplification of RF signals with high linearity and high efficiency at varying power levels, and extends the maximum power capability of the amplifier.

Abstract: An operating voltage applied to a transmitter's power amplifier in a mobile wireless transceiver is dynamically controlled so as to improve the efficiency of the transmitter at all output power levels. In one embodiment, the bias current levels within the transmitter are also varied to optimize the efficiency of the transmitter at all output power levels. In a preferred embodiment, a highly efficient switching regulator is controlled by a control circuit to adjust the operating voltage and/or bias current for the power amplifier in the transmitter. The control circuit has as its input any of a variety of signals which reflect the actual output power of the transmitter, the desired output power, or the output voltage swing of the transmitter.

Abstract: Accordingly, an RF amplifier with reduced power consumption is disclosed. In one embodiment, the RF amplifier includes first and second transistors for amplifying signals. The first transistor has a gate coupled to an input signal source. The second transistor has a gate coupled to the gate of the first transistor for signals in the operating frequency range of the amplifier. The second transistor also has a drain terminal coupled to the drain of the first transistor for signals in the operating frequency range. A first bias voltage generator circuit coupled to the gate of the first transistor provides a first bias voltage to the gate of the first transistor. Likewise, a second bias voltage generator circuit coupled to the gate of the second transistor provides a second bias voltage to the gate of the second transistor. An impedance connected between the source of the second transistor and the drain of the first transistor conducts a bias current.

Abstract: A circuit is provided that solves the problem of implementing a fully balanced (differential) transimpedance amplifier with low-noise and wide bandwidth. This is accomplished by direct coupling the feedback resistors from the outputs of the amplifier to the inputs without the use of a blocking capacitor. The low frequency response is thereby improved and the problems created by a DC bias resistor that degrades the noise performance and, in some case, restricts the dynamic range (caused by pulse width distortion for large signals) are eliminated. The amplifier achieves higher voltage gain than prior designs and also results in lower noise and wider bandwidth. The differential nature of the amplifier provides good power supply rejection. While the preferred embodiment is particularly well-suited to GaAs MESFET technology, the invention can also be applied to silicon bipolar and MOS technology.

Abstract: A circuit is described herein which effectively multiplies the value of a capacitor. The circuit draws current from an input node, where this current being drawn is related to the gain of an amplifier and the value of a capacitor, thus effectively amplifying the capacitance value of a capacitor as seen at the input node.

Abstract: An apparatus and method for improving the bit error rate of multiplexed signals in a multiplexer system includes independently controlling two types of timing errors. The first type of timing error is related to the timing of transitions between alternating portions of the multiplexed output signal. The second type of timing error is related to the amplitude of the crossing points of the multiplexed signal portions. Varying the duty cycle of the clock signal to the multiplexer controls the transition between the alternating portions of the multiplexed output signal, and adding a voltage offset between single-ended components of the multiplexed output signal controls the amplitude of the crossing points between the one/zero and zero/one transitions of the multiplexed outut signal. The two types of timing errors are controlled with two separate control voltage ports that are independently and continuously variable in order to achieve the optimum bit error rate.