Abstract: A tristate output driver circuit (30, 40, 50) includes first (Q7) and second (Q8) switches for selectively connecting a logic high voltage source (VH) or a logic low voltage source (VL) to an output terminal (12) in a first, connected mode. Control nodes (14, 16) on the first and second switches (Q7, Q8) are energized in a precise, symmetrical manner to prevent multiple slopes in the output waveform by a precision input stage (31) that includes cascode outputs (Q17, Q18), cascode current sources (Q19-Q20, Q21-Q22) and bootstrapped current sources (32, 34). In a second, tristate mode, the output terminal (12) is electrically isolated from the logic high (VH) and logic low voltage sources (VL). In the tristate mode, the off-switch remains off and the on-switch is turned off by the precision input stage (31) to minimize glitches in the output waveform.

Abstract: A class AB amplifier comprises a pull-up structure of an E-FET and D-FET connected in parallel and a pull-down structure of an E-FET and D-FET connected in parallel. Use of the E-FETs allows a high peak current to be achieved without increasing the quiescent current to an undesirable level. The pull-up structure and the pull-down structure are driven by currents that are out-of-phase, and accordingly linear push-pull operation is provided.

Abstract: A compensation method and apparatus for enhancing single-ended to differential conversion includes a compensation network that is coupled between the single-ended voltage input and the bias terminal of a differential stage. The compensation network has an impedance substantially equal to the impedance presented by the bias circuit used to bias the differential stage. Accordingly, the compensation network provides a current that substantially cancels the signal tail current supplied to the bias terminal of the differential stage, resulting in a balanced differential output. The compensation network may be AC coupled from the single-ended voltage input to the bias terminal in order to preserve the original DC operating condition. The compensation network may be chosen to provide more cancelling current at higher operating frequencies. Additionally, the compensation network can be configured to match a bias circuit built from resistors, transistors, current mirrors, or the like.

Abstract: A high-gain solid-state amplifier (20) includes an amplification stage including a transistor (Q.sub.1) having a current-dependent transconductance value. The transistor is operatively connected to a load resistor (R.sub.L1) through which a load current (I.sub.1) flows. The value of the load resistor together with the transconductance value affects the voltage gain of the amplifier. A resistor (R.sub.2) provides a supplemental bias current (I.sub.2) to a current summing node (A). The current summing node sums the load current and the supplemental bias current and provides the transistor with a total current (I.sub.d) that affects the transconductance value. The value of the supplemental bias current is chosen to supplement the load current to provide a predetermined total current so that the voltage gain may be adjusted by adjusting the load resistor without changing the transconductance value.

Abstract: A transimpedance amplifier comprises a transconductance amplifier having a nonlinear resistive feedback element. The feedback element includes a pair of resistors and a pair of diodes, one of which conducts (depending upon the voltage polarity) only when the voltage across the diode exceeds the diode on-voltage. This includes additional resistance in the feedback element thereby changing the amplifier gain. The largest value of the resistive feedback element is substantially equal to or less than the output resistance of the transconductance amplifier. The feedback element is both symmetrical and nonlinear. A shunt amplifier is driven by circuit which produces a control signal that varies with a signal current. Increasing signal current increases the DC current shunted from the amplifier input thus decreasing pulse edge distortion and increasing dynamic range. A capacitor AC couples the current input to the amplifier.

Abstract: A high-gain, low noise solid-state multiple stage amplifier (12) includes a phase-inverting input stage (20) and a phase non-inverting output stage (30). The input stage includes a first transistor (Q.sub.1) having a current-dependent transconductance value. The first transistor is operatively connected to a load resistor (R.sub.L1) through which a load current (I.sub.1) flows. An amplified phase-inverted version of a time-varying signal applied to the input (V.sub.i) is developed across the load resistor. The value of the load resistor together with the transconductance value affects the voltage gain of the input stage. A resistor (R.sub.2) provides a supplemental bias current (I.sub.2) to a current summing node (A). The current summing node sums the load current and the supplemental bias current and provides the first transistor with a total current (I.sub.d) that affects the transconductance value.

Abstract: An optical receiver circuit for an incoming optical signal having a variable power level includes an optical detector for receiving the optical signal and generating a current therefrom which varies with the optical signal power level. The current so generated is applied to a transimpedance amplifier. An automatic gain control (AGC) drive circuit is connected around the amplifier thereby increasing its dynamic range. The AGC drive circuit drives a FET which has one side thereof connected to the transimpedance amplifier for shunting current from the input thereof. A negative feedback circuit comprising an amplifier is connected across the FET, which comprises the resistive feedback element, thus reducing the FET resistance by a factor of 1+T, where T is the feedback circuit loop gain.

Abstract: A high-impedance FET circuit in which the anode of a diode is electrically connected to the first side of the FET and the diode's cathode is connected to the FET gate. The diode biases the FET to reduce second side current when the second side is at a positive potential relative to the diode cathode. Such circuits placed back-to-back accommodate signals of both polarities and are used as a high impedance element in a low-pass filter implemented in an integrated circuit. An equivalent symmetrical circuit implemented with two enhancement FETs is also disclosed.

Abstract: A binarily weighted FET attenuator implemented in integrated form. The resistance of the vertical branches to the horizontal branches is at a ratio of 2:1. Each vertical branch includes a FET switch for switching between ground and a summing amplifier and each horizontal branch includes a FET permanently biased to conduct. Thus, variations in the value of r.sub.on, the resistance of each FET when conducting, due to fabrication process and temperature are compensated for due to the presence of FETs in both the vertical and horizontal legs of the attenuator.

Abstract: A solid-state electrical circuit (10) includes a reference diode (D1) and multiple diodes (D3-D14) connected in electrical series to produce a substantially temperature-invariant output reference voltage. The reference diode is characterized by a forward voltage drop (V.sub.D1) that changes in accordance with a temperature coefficient. The multiple diodes, which have selected junction areas (A1 and A2) and receive one of two different forward-bias currents (I1 and I2), are electrically interconnected to establish a net voltage (.DELTA.V.sub.Di) that equals the forward voltage drop across the reference diode and changes in accordance with a net temperature coefficient of substantially equal magnitude but of opposite sign to the temperature coefficient of the reference diode. The output reference voltage equals the sum of the forward voltage drop across the reference diode and the net voltage established by the multiple diodes.

Abstract: A class AB amplifier output circuit having two output devices is implemented using single polarity GaAs devices. The exemplified circuit comprises a bias control loop that includes the gate-to-source voltage of one of the output devices, the gate-to-source voltage of a device that the replicates the gate-to-source voltage of the other output device, and a pair of diodes. The configuration of the control loop is such that the bias current in the two output devices is controlled and set to approximately one quarter of I.sub.DSS. The output circuit has a differential input that may be coupled to the output of a preamplifier circuit in a conventional manner.

Abstract: An output stage for producing a high accuracy differential output signal includes a first differential amplifier providing a pair of single-ended first signals of magnitudes that swing in opposite directions between first and second levels following a change in level of an input signal. A sum of magnitudes of the first signals is controlled by an input control current. The first signals provide input to a second differential amplifier supplying a pair of single-ended second signals swinging in opposite directions between third and fourth levels when the first signals change levels, the second signals forming the differential output signal of the output stage. An indicating signal, provided by the second differential amplifier, supplies a measure of a sum of magnitudes of the second signals. A third differential amplifier produces the control current of magnitude determined by a magnitude difference between the indicating signal and a constant reference signal.

Abstract: A tristate output circuit includes a pair of transistors having sources connected to a switchable current source and drains separately coupled to a voltage source through separate resistors and switching transistors. When the current source and switching transistors are on, the circuit operates in a back termination mode wherein it amplifies a differential input signal applied across the gates of the transistor pair to produce a differential output signal across their drains for transmission on a transmission line. The load resistors are sized to match the characteristic impedance of a transmission line so as to properly terminate the transmission line. In an open drain mode, the switching transistors are off, uncoupling the drains of the transistor pair from the voltage source so as to increase output impedance. In a tristate mode, the current source and switching transistors are turned off, thereby turning off the transistor pair and rendering the output impedance of the circuit substantially infinite.

Abstract: A limiter circuit comprises a first and second differential transistor amplifiers, with the collectors of the transistors of the second amplifier receiving the outputs of the first amplifier. A high gain amplifier has its inverting and non-inverting inputs connected to the output of the first differential amplifier, and has its output connected to the base of one of the transistors of the second amplifier through a feedback network. The differential amplifiers have respective current sources, the current sources of the second amplifier providing a larger current than that of the first amplifier.

Abstract: A current source provides an output current whose magnitude is substantially independent of changes in temperature. In each of three embodiments (50, 100, 120), one or more bipolar transistors are employed to provide a compensating current which is dependent on the base-to-emitter voltages, V.sub.BE, of such bipolar transistors. The compensating current changes with temperature so as to offset changes in the uncompensated output current so that the total output current is substantially independent of V.sub.BE. The three embodiments employ current mirror circuits (10, 122) that provide a current source of simple circuit design that is operable with the use of a single power supply at a relatively low voltage.

Abstract: A digital-to-analog converter circuit (10) comprises a current switch (22) that has differential input conductors (16a, 16b, . . . , 16n and 18a, 18b, . . . , 18n) which receive complementary logic voltage signals corresponding to a digital input word (X.sub.1, X.sub.2, . . . , X.sub.n). The current switch synthesizes an output signal (V.sub.o -V.sub.o) whose magnitude corresponds to the weighted value of the digital input word. The circuit further comprises a current reference source (60) that develops a reference current (I.sub.REF) from which transistor constant-current sources (48a, 48b, . . . , 48n) in the current switch derive binary-weighted currents to synthesize the output voltage signal. The current reference source includes an impedance element or resistor (70) through which the reference current flows and which is scaled to the load impedance connected to the current switch.

Abstract: A frequency-compensated transistor feedback amplifier provides relatively wide bandwidth and relatively large phase and gain margins, irrespective of the transconductance of the transistors in the amplifier. Each one of three preferred embodiments (10, 50, 104) of the invention includes a transconductance stage (20, 68, 68) and an amplifier stage (12 and 14, 54, 54 and 14). The transconductance stage delivers an input signal to the amplifier stage, which produces an amplified replica of the input signal. A feedback capacitor (24, 88, 24 and 88) connected between the output and the input of the amplifier stage provides dominant pole compensation by which the magnitude of the loop gain diminishes by 6 dB/octave with increasing frequency. The capacitor provides a forward feedthrough path for any residual portion of the input signal so that the residual portion arrives at the output of the amplifier stage in substantially the same phase relation with that of the output signal of intermediate frequency.

Abstract: A current mirror includes first and second transistors having interconnected bases and having emitters respectively coupled through first and second resistors to a common potential source. A collector voltage of the first transistor is fed back to the transistor bases through a feedback capacitor, and through a unity gain amplifier and series resistor, to form a feedback loop for controlling the voltage at the transistor bases. A current source connected to the collector of the first transistor causes the second transistor to produce an output collector current substantially equal in magnitude to the input current. To prevent circuit instability, the feedback capacitor and the aforementioned series resistor are sized to reduce the frequency at which the open loop gain of the feedback loop is unity so that it does not exceed the short-circuit current gain-bandwidth product of the first transistor.

Abstract: A high-speed, supply independent level shifter is implemented in bipolar, JFET, MOSFET or MESFET integrated circuit technology. A level shift circuit having a desired input potential V.sub.1 and a required output potential V.sub.2, is incorporated into a first current leg connected between first and second supply voltages. A second current leg in parallel with the first leg establishes a reference current. The two current legs are coupled by a current mirror to establish a fixed, preferably equal, relationship between the currents in the two legs. Each current leg includes a reference resistor. A buffered, floating voltage source is coupled in series with the resistor in the first leg to the control conductor of the current mirror. The voltage source is designed and the resistor values selected to provide a potential V.sub.3 that is an additive function of potentials V.sub.1 and V.sub.2 such that V.sub.1 is independent of the supply voltages.

Abstract: In an integrated circuit, a reference voltage proportional to the pinchoff voltage of a field effect transistor is created by providing a current source, including a first depletion-mode FET, and a second depletion mode FET having a source connected to the drain of the first FET at an output node. The first and second FETs have their source and drain, respectively, connected to the first and second supply voltages, respectively, so that in operation, substantially equal currents flow through the two transistors. The FETs are biased to operate in saturation. Regarding the first FET, this current is equal to I.sub.DSS (defined as I.sub.D when V.sub.GS =0) of the first FET (I.sub.DSS1) and is not greater than, and usually less than, I.sub.DSS of the second FET (I.sub.DSS2). The dimensions of the FETs are proportioned such that the gate-source voltage across the second FET substantially equals a constant times the pinchoff voltage.