Patents by Inventor Stuart B. Molin
Stuart B. Molin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8748245Abstract: An integrated circuit fabricated on a semiconductor-on-insulator transferred layer is described. The integrated circuit includes an interconnect layer fabricated on the back side of the insulator. This interconnect layer connects active devices to each other through holes etched in the insulator. This structure provides extra layout flexibility and lower capacitance, thus enabling higher speed and lower cost integrated circuits.Type: GrantFiled: March 27, 2013Date of Patent: June 10, 2014Assignee: IO Semiconductor, Inc.Inventors: Michael A. Stuber, Stuart B. Molin, Chris Brindle
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Publication number: 20140035129Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.Type: ApplicationFiled: December 21, 2012Publication date: February 6, 2014Applicant: IO SEMICONDUCTOR, INC.Inventors: Michael A. Stuber, Stuart B. Molin, Mark Drucker, Peter Fowler
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Publication number: 20140009135Abstract: A charge pump regulator circuit includes a voltage controlled oscillator and a plurality of charge pumps. The voltage controlled oscillator has a plurality of inverter stages connected in series in a ring. A plurality of oscillating signals is generated from outputs of the inverter stages. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive voltage. Each oscillating signal is phase shifted from a preceding oscillating signal. Each charge pump is connected to a corresponding one of the inverter stages to receive the oscillating signal produced by that inverter stage. Each charge pump outputs a voltage and current. The output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to the load.Type: ApplicationFiled: July 9, 2012Publication date: January 9, 2014Applicant: IO SEMICONDUCTOR, INC.Inventors: Stuart B. Molin, Perry Lou, Clint Kemerling
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Publication number: 20140009136Abstract: A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.Type: ApplicationFiled: July 8, 2013Publication date: January 9, 2014Inventors: Stuart B. Molin, Perry Lou, Clint Kemerling
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Publication number: 20130344680Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.Type: ApplicationFiled: August 28, 2013Publication date: December 26, 2013Applicant: IO SEMICONDUCTOR, INC.Inventors: Anton Arriagada, Michael A. Stuber, Stuart B. Molin
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Publication number: 20130280884Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.Type: ApplicationFiled: June 17, 2013Publication date: October 24, 2013Inventors: Chris Brindle, Michael A. Stuber, Stuart B. Molin
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Patent number: 8536021Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.Type: GrantFiled: November 26, 2012Date of Patent: September 17, 2013Assignee: IO Semiconductor, Inc.Inventors: Anton Arriagada, Michael A. Stuber, Stuart B. Molin
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Publication number: 20130228855Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.Type: ApplicationFiled: April 4, 2013Publication date: September 5, 2013Applicant: IO SEMICONDUCTOR, INC.Inventors: Stuart B. Molin, Michael A. Stuber
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Patent number: 8497670Abstract: A charge pump regulator circuit includes a voltage controlled oscillator and a plurality of charge pumps. The voltage controlled oscillator has a plurality of inverter stages connected in series in a ring. A plurality of oscillating signals is generated from outputs of the inverter stages. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive voltage. Each oscillating signal is phase shifted from a preceding oscillating signal. Each charge pump is connected to a corresponding one of the inverter stages to receive the oscillating signal produced by that inverter stage. Each charge pump outputs a voltage and current. The output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to the load.Type: GrantFiled: December 19, 2012Date of Patent: July 30, 2013Assignee: IO Semiconductor, Inc.Inventors: Stuart B. Molin, Perry Lou, Clint Kemerling
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Patent number: 8466054Abstract: A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.Type: GrantFiled: December 5, 2011Date of Patent: June 18, 2013Assignee: IO Semiconductor, Inc.Inventors: Michael A. Stuber, Chris Brindle, Stuart B. Molin
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Patent number: 8466036Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.Type: GrantFiled: December 7, 2011Date of Patent: June 18, 2013Assignee: IO Semiconductor, Inc.Inventors: Chris Brindle, Michael A. Stuber, Stuart B. Molin
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Patent number: 8426888Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.Type: GrantFiled: October 11, 2011Date of Patent: April 23, 2013Assignee: IO Semiconductor, Inc.Inventors: Stuart B. Molin, Michael A. Stuber
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Patent number: 8426258Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.Type: GrantFiled: October 11, 2011Date of Patent: April 23, 2013Assignee: IO Semiconductor, Inc.Inventors: Stuart B. Molin, Michael A. Stuber
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Patent number: 8357975Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.Type: GrantFiled: April 28, 2012Date of Patent: January 22, 2013Assignee: IO Semiconductor, Inc.Inventors: Michael A. Stuber, Stuart B. Molin, Paul A. Nygaard
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Publication number: 20120211835Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.Type: ApplicationFiled: April 28, 2012Publication date: August 23, 2012Applicant: IO SEMICONDUCTOR, INC.Inventors: Michael A. Stuber, Stuart B. Molin, Paul A. Nygaard
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Publication number: 20120205725Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.Type: ApplicationFiled: April 21, 2012Publication date: August 16, 2012Applicant: IO SEMICONDUCTOR, INC.Inventors: Paul A. Nygaard, Stuart B. Molin, Michael A. Stuber
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Patent number: 8232597Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.Type: GrantFiled: July 14, 2010Date of Patent: July 31, 2012Assignee: IO Semiconductor, Inc.Inventors: Michael A. Stuber, Stuart B. Molin, Paul A. Nygaard
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Publication number: 20120161310Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.Type: ApplicationFiled: December 7, 2011Publication date: June 28, 2012Applicant: IO SEMICONDUCTOR, INC.Inventors: Chris Brindle, Michael A. Stuber, Stuart B. Molin
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Publication number: 20120146193Abstract: A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.Type: ApplicationFiled: December 5, 2011Publication date: June 14, 2012Applicant: IO SEMICONDUCTOR, INC.Inventors: Michael A. Stuber, Chris Brindle, Stuart B. Molin
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Publication number: 20120088339Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.Type: ApplicationFiled: October 11, 2011Publication date: April 12, 2012Applicant: IO SEMICONDUCTOR, INC.Inventors: Stuart B. Molin, Michael A. Stuber