Abstract: A method of manufacturing a semiconductor structure includes providing a substrate, disposing a first semiconductive material over the substrate at a first temperature, disposing a second semiconductive material over the first semiconductive material at a second temperature, and disposing a third semiconductive material over the second semiconductive material at a third temperature, wherein a first interval between the first temperature and the second temperature is substantially same as a second interval between the second temperature and the third temperature.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

Abstract: A multi-chamber furnace for processing at least 100 substrates is provided. Reactor housings define a plurality of laterally spaced reactor chambers that are individually configured to accommodate up to about 50 substrates. Substrate holders correspond to the reactor chambers, and are configured to support and vertically stack substrates arranged in the corresponding reactor chambers. Heaters correspond to the reactor chambers and are configured to heat the corresponding reactor chambers. A method for batch processing substrates using the multi-chamber furnace is also provided.

Abstract: Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.

Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate and heating the flowable layer to form a cured layer in a curing process. In addition, the curing process is performed under a pressure of over 2 atmospheres, and the flowable layer reacts with precursors in the flowable layer during the curing process.

Abstract: The present disclosure relates to an electro-chemical plating (ECP) process that provides for an isotropic deposition, and a related apparatus. In some embodiments, the disclosed ECP process is performed by providing a substrate into an electroplating solution comprising a plurality of ions of a material to be deposited. A periodic patterned signal, which alternates between a first value and a different second value, is applied to the substrate. When the periodic patterned signal is at the first value, ions from the electroplating solution affix to the substrate. When the periodic patterned signal is at the second value, ions from the electroplating solution do not affix to the substrate. By using the periodic patterned signal to perform electro-chemical plating, the deposition rate of the plating process is reduced, resulting in an isotropic deposition over the substrate that mitigates gap fill problems (e.g., void formation).

Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate and heating the flowable layer to form a cured layer in a curing process. In addition, the curing process is performed under a pressure of over 2 atmospheres, and the flowable layer reacts with precursors in the flowable layer during the curing process.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer. The high k dielectric layer is partially crystallized and comprising an average thickness of from about 10 ? to about 30 ?. Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (i) forming a high k dielectric layer with a thickness of from about 10 ? to about 30 ? over a substrate, (ii) forming a gate layer over the dielectric layer, and (iii) transforming at least a portion of the dielectric layer from a first phase to a second phase by microwave irradiation.

Abstract: The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to from a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.

Abstract: A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer.

Abstract: The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to from a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer. The high k dielectric layer is partially crystallized and comprising an average thickness of from about 10 ? to about 30 ?. Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (i) forming a high k dielectric layer with a thickness of from about 10 ? to about 30 ? over a substrate, (ii) forming a gate layer over the dielectric layer, and (iii) transforming at least a portion of the dielectric layer from a first phase to a second phase by microwave irradiation.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

Abstract: Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharged assembly that is adjacent to the stage. The discharged assembly includes a discharged passage configured without a vertical flow path section.

Abstract: A metrology device includes a light source and an image sensor. The light source is configured for providing an X-ray illuminating a wafer. The image sensor is configured for detecting a spatial domain pattern produced when the X-ray illuminating the wafer.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

Abstract: The present disclosure relates to an electro-chemical plating (ECP) process that provides for an isotropic deposition, and a related apparatus. In some embodiments, the disclosed ECP process is performed by providing a substrate into an electroplating solution comprising a plurality of ions of a material to be deposited. A periodic patterned signal, which alternates between a first value and a different second value, is applied to the substrate. When the periodic patterned signal is at the first value, ions from the electroplating solution affix to the substrate. When the periodic patterned signal is at the second value, ions from the electroplating solution do not affix to the substrate. By using the periodic patterned signal to perform electro-chemical plating, the deposition rate of the plating process is reduced, resulting in an isotropic deposition over the substrate that mitigates gap fill problems (e.g., void formation).

Abstract: Atomic layer deposition (ALD) techniques typically involve briefly exposing the surface of a substrate to a precursor within an atomic layer deposition chamber, and purging the chamber with a purge gas, such as nitrogen, before exposing the substrate to a second precursor. A series of such cycles results in the deposition of microscopically thin film layers on the substrate surface that are further processed to generate a semiconductor component. In order to reduce unintended oxygen deposition, the chamber is typically evacuated to a vacuum level of 10e?06 torr-liters/second, which is suitable for the related techniques of chemical vapor deposition. However, atomic layer deposition is demonstrably more sensitive to oxygen contamination, due to the exposure of each layer to residual oxygen within the chamber. Tighter process control is achievable by performing atomic layer deposition at a higher vacuum level, not exceeding approximately 10e?06 torr-liters/second, in order to reduce oxygen contamination.