Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

Abstract: A quinonemethide triterpenoid is administered to subjects with multidrug-resistant cancer, in particular a cancer with enhanced expression and/or functional activity of ABC transporter proteins such as P-glycoprotein and/or an apoptosis-deficient, in particular p53-, Bax- or Bak-deficient, cancer, i.e. specific subgroups of subjects with cancer. The quinonemethide triterpenoid is suitable to treat cancer allowing for an accumulation of cytotoxic or therapeutic compounds in the cells while having exceptionally increased cytotoxic activity towards the multidrug-resistant cancer cells and while allowing for an increased activity of chemotherapeutic compounds. Methods for specifically targeting cancer cells with multidrug-resistance and methods for potentiating the activity of a chemotherapeutic compound in those cancer cells are also disclosed. A kit including a quinonemethide triterpenoid and a chemotherapeutic compound is also provided.

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Abstract: A control method for a first device of an inter-integrated circuit (I2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I2C system when determining that the status information of the first device matches the target status.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

Abstract: A brake mechanism has a brake disk, multiple clutches, and multiple brake assemblies. The brake disk is coaxially connected to a rotatable work table. The multiple clutches are capable of clamping the brake disk. The multiple brake assemblies correspond in position to the multiple clutches. Each one of the multiple brake assemblies has a housing, an abutting shaft inserted in the housing, and multiple elastic units received in the housing and abutting against the abutting shaft. The multiple abutting shafts of the multiple brake assemblies abut against the brake disk for stopping the work table from rotating. A hydraulic system applies hydraulic pressure inside the multiple housings of the multiple brake assemblies and forces the multiple abutting shafts to depart from the corresponding clutch, making the work table rotate again.

Abstract: A brake mechanism has a brake disk, multiple clutches, and multiple brake assemblies. The brake disk is coaxially connected to a rotatable work table. The multiple clutches are capable of clamping the brake disk. The multiple brake assemblies correspond in position to the multiple clutches. Each one of the multiple brake assemblies has a housing, an abutting shaft inserted in the housing, and multiple elastic units received in the housing and abutting against the abutting shaft. The multiple abutting shafts of the multiple brake assemblies abut against the brake disk for stopping the work table from rotating. A hydraulic system applies hydraulic pressure inside the multiple housings of the multiple brake assemblies and forces the multiple abutting shafts to depart from the corresponding clutch, making the work table rotate again.

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k?h, so that ?k/n? hard IP blocks provide h=n*p available hard IP data lanes. In that case, h?k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

Abstract: A polyphase power dispatching system and a polyphase power dispatching method are provided. The polyphase power dispatching system includes an electric meter, a single-phase electricity storage module, a switch and a control circuit. The electric meter can measure transmission statuses of power transmission lines of a polyphase power line group. The common terminal of the switch is connected to the single-phase electricity storage module. The selection terminals of the switch are connected to the power transmission lines in a one-to-one manner. The control circuit is connected to the electric meter and the switch. The control circuit can correspondingly control the switch based on the transmission status of each power transmission line, so that the switch selectively connects the single-phase electricity storage module to one of the power transmission lines.

Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.