Patents by Inventor Subhadeep Kal
Subhadeep Kal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12261053Abstract: Etching is selectively performed and selectively is modified using a treatment or pre-treatment with nitrogen radicals, prior to etching. Etching is performed with a gas phase chemistry etch. Different selectivities can also be provided in different processes or different regions (or different devices or different locations) of a substrate by the selective use and non-use of the treatment.Type: GrantFiled: August 10, 2022Date of Patent: March 25, 2025Assignee: Tokyo Electron LimitedInventors: Ivo Otto, IV, Subhadeep Kal
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Patent number: 12261054Abstract: An etch and surface modification is performed in a plasma, in which ions have been removed so that radicals of the plasma form a modified surface of a layer of substrate. A gas chemistry is reacted with the modified surface to form a reacted modified surface, and the reacted modified surface is removed.Type: GrantFiled: August 11, 2022Date of Patent: March 25, 2025Assignee: Tokyo Electron LimitedInventors: Ivo Otto, IV, Subhadeep Kal
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Publication number: 20250069896Abstract: A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.Type: ApplicationFiled: August 22, 2023Publication date: February 27, 2025Inventors: Ivo Otto IV, Toshiki Kanaki, Jonathan Hollin, Subhadeep Kal
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Publication number: 20250054809Abstract: A method of processing a substrate that includes: forming a pattern of an electrically conductive layer over the substrate, the electrically conductive layer and a first dielectric layer being exposed at a surface of the substrate; selectively depositing a graphene layer over the electrically conductive layer relative to the first dielectric layer; selectively depositing a second dielectric layer over the first dielectric layer relative to the graphene layer; and depositing a third dielectric layer over the substrate, the third dielectric layer covering the second dielectric layer and the graphene layer.Type: ApplicationFiled: August 7, 2023Publication date: February 13, 2025Inventors: Kandabara Tapily, Subhadeep Kal, Peng Wang, Peter Biolsi
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Publication number: 20240405022Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a first fin structure and a second fin structure in a first region and a second region of a substrate, respectively, wherein the first and second fin structure and the substrate comprise a first semiconductor material; forming a first liner structure and a second liner structure at least extending along sidewalls of the first fin structure and sidewalls of the second fin structure, respectively; replacing an upper portion of the second fin structure with a second semiconductor material, while leaving the first fin structure substantially intact; and exposing a top surface and upper sidewalls of the first fin structure, and a top surface and upper sidewalls of the second fin structure.Type: ApplicationFiled: May 31, 2023Publication date: December 5, 2024Applicant: Tokyo Electron LimitedInventors: Eric Chih-Fang LIU, Subhadeep KAL, Peter WANG, Ying TRICKETT, Ya-Ming CHEN
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Publication number: 20240304500Abstract: Aspects of the present disclosure provide a method for fabricating a forksheet semiconductor structure. For example, the method can include forming on a substrate a multi-layer stack including first and second semiconductor layers stacked over one another alternately, forming a cap layer over the multi-layer stack, forming a mandrel structure from the multi-layer stack and the cap layer, forming a fill material that surrounds the mandrel structure and has a top surface level with a top of the mandrel structure, partially recessing the cap layer to uncover opposite inner sidewalls of the fill material, forming sidewall spacers on the opposite inner sidewalls, directionally etching the multi-layer stack to define an insulation wall trench using the sidewall spacers as an etch mask, and forming an insulation material within the insulation wall trench to form an insulation wall that separates the multi-layer stack into insulated first and second multi-layer stacks.Type: ApplicationFiled: March 6, 2023Publication date: September 12, 2024Applicant: Tokyo Electron LimitedInventors: Eric Chih-Fang LIU, Subhadeep KAL, Kai-Hung YU, Shihsheng CHANG
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Publication number: 20240128088Abstract: Methods for selective etching of one layer or material relative to another layer or material adjacent thereto. In an example, a SiGe layer is etched relative to or selective to another silicon containing layer which either contains no germanium or geranium in an amount less than that of the target layer.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: TOKYO ELECTRON LIMITEDInventors: Toshiki KANAKI, Subhadeep KAL, Aelan MOSDEN, lvo OTTO, IV, Masashi MATSUMOTO, Shinji IRIE
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Publication number: 20240096639Abstract: A surface of a substrate is modified, where the substrate includes at least two different layers or films of different materials. The modified layer is then selectively converted to a protection layer on one of the layers, while the other layer is etched.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Applicant: TOKYO ELECTRON LIMITEDInventors: Jonathan HOLLIN, Matthew Flaugh, Subhadeep Kal, Aelan Mosden
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Publication number: 20240055268Abstract: Etching is selectively performed and selectively is modified using a treatment or pre-treatment with nitrogen radicals, prior to etching. Etching is performed with a gas phase chemistry etch. Different selectivities can also be provided in different processes or different regions (or different devices or different locations) of a substrate by the selective use and non-use of the treatment.Type: ApplicationFiled: August 10, 2022Publication date: February 15, 2024Applicant: TOKYO ELECTRON LIMITEDInventors: Ivo Otto, IV, Subhadeep Kal
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Publication number: 20240055270Abstract: An etch and surface modification is performed in a plasma, in which ions have been removed so that radicals of the plasma form a modified surface of a layer of substrate. A gas chemistry is reacted with the modified surface to form a reacted modified surface, and the reacted modified surface is removed.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: TOKYO ELECTRON LIMITEDInventors: Ivo Otto, IV, Subhadeep Kal
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Publication number: 20230360921Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.Type: ApplicationFiled: October 12, 2022Publication date: November 9, 2023Applicant: TOKYO ELECTRON LIMITEDInventors: Matthew FLAUGH, Jonathan HOLLIN, Subhadeep KAL, Pingshan LUAN, Hamed HAJIBABAEINAJAFABADI, Yu-Hao TSAI, Aelan MOSDEN
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Patent number: 11715643Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.Type: GrantFiled: June 2, 2020Date of Patent: August 1, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Subhadeep Kal, Daisuke Ito, Matthew Flaugh, Yusuke Muraki, Aelan Mosden
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Patent number: 11631671Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.Type: GrantFiled: December 29, 2020Date of Patent: April 18, 2023Assignee: Tokyo Electron LimitedInventors: H. Jim Fulford, Anton J. Devilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann, Subhadeep Kal
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Publication number: 20230036597Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.Type: ApplicationFiled: August 1, 2022Publication date: February 2, 2023Applicant: Tokyo Electron LimitedInventors: Jeffrey SMITH, Daniel CHANEMOUGAME, Lars LIEBMANN, Paul GUTWIN, Subhadeep KAL, Kandabara TAPILY, Anton DEVILLIERS
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Patent number: 11557479Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.Type: GrantFiled: March 19, 2020Date of Patent: January 17, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Eric Chih-Fang Liu, Akiteru Ko, Subhadeep Kal, Toshiharu Wada
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Publication number: 20220416048Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.Type: ApplicationFiled: June 28, 2022Publication date: December 29, 2022Applicant: Tokyo Electron LimitedInventors: Jeffrey SMITH, Lars LIEBMANN, Daniel CHANEMOUGAME, Paul GUTWIN, Kandabara TAPILY, Subhadeep KAL, Robert CLARK
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Patent number: 11538691Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.Type: GrantFiled: March 31, 2021Date of Patent: December 27, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Subhadeep Kal, Nihar Mohanty, Angelique D. Raley, Aelan Mosden, Scott W. Lefevre
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Patent number: 11444082Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.Type: GrantFiled: September 30, 2020Date of Patent: September 13, 2022Assignee: Tokyo Electron LimitedInventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink
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Patent number: 11424123Abstract: In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.Type: GrantFiled: April 17, 2020Date of Patent: August 23, 2022Assignee: Tokyo Electron LimitedInventors: Eric Chih-Fang Liu, Akiteru Ko, Angelique Raley, Henan Zhang, Shan Hu, Subhadeep Kal
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Patent number: 11380554Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.Type: GrantFiled: February 11, 2020Date of Patent: July 5, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Subhadeep Kal, Nihar Mohanty, Angelique D. Raley, Aelan Mosden, Scott W. Lefevre