Abstract: A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.

Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

Abstract: A method for forming an L-shaped spacer using disposable polysilicon top spacers. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. A disposable polysilicon top spacer layer is formed on the dielectric spacer layer. The disposable polysilicon top spacer layer is anisotropically etched to form disposable polysilicon top spacers. The dielectric spacer layer is etched to form L-shaped dielectric spacers, using the disposable polysilicon top spacers as an etch mask. The disposable polysilicon top spacers are removed leaving an L-shaped dielectric spacer. In one embodiment, lightly doped source and drain regions are formed prior to forming the liner oxide layer and the L-shaped spacers.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A method for forming dual-damascene type conducting interconnects with nonmetallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A method and system for providing a via structure for an integrated circuit is disclosed. The method and system includes providing a high conductivity metal that forms a metal structure consisting of the high conductivity metal. The method and system also includes a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole. The method and system also include providing a via plug material other than the high conductivity metal. The via plug material covers the high conductivity metal and substantially fills the via hole. The via plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is for gettering the high conductivity metal sputtered on the sidewalls of the via hole.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

Abstract: A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.

Abstract: A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer.

Abstract: A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer.

Abstract: An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.

Abstract: A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution comprising an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a novel alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.

Abstract: A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

Abstract: A method of preparing a narrow photoresist line by first forming a resist pattern on a substrate, wherein a resist line is designed to have a width “w” in excess of a desired width “w1” The resist is then subjected to ionic bombardment with ionized particles in a direction normal to the planar surface of a resistant substrate. The ionic bombardment causes formation of a hardened “chemically less reactive” skin on the exposed top surface of the photoresist. The resist is then subjected to an isotropic etch procedure. Due to the hardened top surface of the narrow pattern, the side wall erode at a faster rate than the top, causing a narrowing of the line width, while retaining a more substantial photoresist thickness than would occur if the top surface would not be hardened in advance of the etch procedure.

Abstract: A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted.