Abstract: An apparatus and method for solving a system of linear equations uses a sequence of matrix-vector multiplications wherein the matrix to be multiplied is derived from an expansion point matrix that permits rapid convergence. The matrix-vector multiplication form of the sequence permits calculations to be performed on a network of parallel processors.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings.

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material.

Abstract: A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.

Abstract: Technique and apparatus for planarizing microsteps on a substrate by compressing the surface to be smoothed against a frozen layer of an etchant, where the compressive force is sufficient to melt the etchant at the contact edges between said microsteps and said etchant.

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.

Abstract: A method for rapid anisotropic dry etching of oxide compounds in high aspect ratio openings which etching method is highly selective to metal salicides and which method employs plasma gases of CHF.sub.3, N.sub.2 and a high flow rate of He at a high pressure and products made by the process.

Abstract: An improved SiO.sub.x etch which employs CHF.sub.3, N.sub.2 and a light mass cooling gas in total pressure on the order of 3000 mT in a confined plasma reactor. High aspect ratios at least 10:1 are obtainable.

Abstract: An etch stop layer (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

Abstract: Technique and apparatus for planarizing microsteps on a substrate by compressing the surface to be smoothed against a frozen layer of an etchant, where the compressive force is sufficient to melt the etchant at the contact edges between said microsteps and said etchant.

Abstract: An apparatus and method for performing matrix calculations is provided. The apparatus comprises a computer system having a linearly connected array of processors. Each processor has three inputs, two of which receive data along the linear array. The processors are configured to perform certain multiply-add operations. The methods permit speeded up solution of systems of linear equations and matrix inversion. The methods involve manipulating the matrices and the unknown vector values such that the problem can be solved using vector orthogonalization techniques.

Abstract: A method for measuring the sidewall angle of patterned photoresist (16), as well as wall angles of other materials, is provided. The method comprises forming two copies of the patterned photoresist feature for which the sidewall measurement is to be obtained on a conducting substrate (14). The first copy is processed via conventional techniques for linewidth measurement, which consists of a pattern transfer etch of the first copy into the underlying conductive substrate, followed by electrical measurement of the conductor linewidth to yield linewidth 1 (LW1). The second copy is processed such that there is a shape altering etch prior to the pattern transfer etch. A linewidth 2 (LW2) is obtained. The angle is then extracted from the two linewidth measurements.

Abstract: Method and apparatus for a demand scheduled partial carrier load planning system for the transportation industry, designed to distribute planned and random orders, each order having a source point and a destination point in the territory served, and for distributing products and materials in a predetermined geographic territory, primarily intended for use in connection with wheeled vehicles traveling over public highways.

Abstract: A mechanism and method for calendaring a plurality of events such as scheduling the operation of interrelated machines which perform a process flow. Future time is divided into segments, called buckets, of increasing length. The first two buckets are of the same size and each of the following buckets twice as large as its preceding bucket. The first bucket slides so as to always cover a specified length of time following the current time. Events scheduled in the calendar is added to the appropriate bucket, depending on how far in the future it is to take place. When the current time equals the scheduled time for an event, then that event is removed from the bucket where it resides. When a bucket has become empty because all events have been removed from it, the events in the following bucket are distributed over the two buckets preceding it.

Abstract: An airline reservation system implemented using a computer wherein reservations are controlled by a seat inventory control system. The inventory control system produces optimal reservation control using network-wide booking limits while taking into account the probabilistic nature of demand. The inventory control system, based on a concept termed Network-Based Expected Marginal Seat Revenue (EMSR), does not require the large number of variables required by the other network-based approaches, and it incorporates a probabilistic demand model without resorting to computationally intractable integer programming.