Patents by Inventor Subramanian S. Iyer

Subramanian S. Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225749
    Abstract: A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.
    Type: Application
    Filed: November 1, 2018
    Publication date: July 22, 2021
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa
  • Publication number: 20210074648
    Abstract: A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: March 11, 2021
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Subramanian S. IYER, Arsalan ALAM, Amir HANNA, Takafumi FUKUSHIMA
  • Patent number: 10930601
    Abstract: A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 23, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Subramanian S. Iyer, Takafumi Fukushima, Adeel A. Bajwa
  • Publication number: 20200406039
    Abstract: A spinal cord stimulator includes: (1) a flexible substrate; (2) a power source embedded in the flexible substrate; (3) a controller embedded in the flexible substrate and connected to the power source; and (4) an array of electrodes, including an array of stimulation electrodes, disposed over the flexible substrate and connected to the controller, wherein the controller is configured to direct the array of stimulation electrodes to deliver a stimulation pattern to a spinal cord of a patient.
    Type: Application
    Filed: March 15, 2019
    Publication date: December 31, 2020
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Bilwaj Gaonkar, Steven L. Moran, Amir Hanna, Luke Macyszyn, Subramanian S. Iyer
  • Publication number: 20200403293
    Abstract: A system is provided for interconnecting multiple functional dies on a single substrate, including: (1) multiple global links in the substrate; (2) multiple local links in the substrate; and (3) multiple utility dies on the substrate, wherein each of the utility dies is connected to at least one of the global links, the utility dies are configured to communicate with one another through the global links, each of the utility dies is connected to at least one of the local links and is configured to communicate with at least one of the functional dies through the at least one of the local links. In some embodiments, an antenna is integrated into the substrate.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa, Arpan Dasgupta, Arsalan Alam
  • Patent number: 10740282
    Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10657231
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 10613754
    Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
  • Patent number: 10585643
    Abstract: A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 10, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xuefeng Gu, Subramanian S. Iyer
  • Publication number: 20200074051
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Publication number: 20200042182
    Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
  • Patent number: 10503402
    Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
  • Publication number: 20190287927
    Abstract: A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.
    Type: Application
    Filed: October 30, 2017
    Publication date: September 19, 2019
    Inventors: Subramanian S. IYER, Takafumi FUKUSHIMA, Adeel A. BAJWA
  • Patent number: 10342060
    Abstract: In a communication system where a primary cell is controlled by a first base station and a secondary cell is controlled by a second, different base station, flow control is performed between the primary cell and the secondary cell for data for a radio link control layer. According to the flow control, the data for the radio link control layer is communicated between the first and second base stations using a link between the first and second base stations. Flow control may be performed between the primary cell and the secondary cell by dynamically controlling a depth of queued radio link control data in the secondary cell for one or more UEs based on one or more factors, e.g., current/future loading of secondary cell, peak theoretical throughput for a UE in the secondary cell, and/or a UE's current channel quality information. Apparatus, methods, and computer program products are disclosed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 2, 2019
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Subramanian S. Iyer, Mark Marsan, Kirk Ingemunson, Apurv Mathur
  • Publication number: 20190155999
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 10262119
    Abstract: An authenticating service of a chip having an intrinsic identifier (ID) is provided. The authenticating device includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Publication number: 20180189233
    Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arhur, John E. Barth, JR., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Publication number: 20180136846
    Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 17, 2018
    Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
  • Publication number: 20180124851
    Abstract: In a communication system where a primary cell is controlled by a first base station and a secondary cell is controlled by a second, different base station, flow control is performed between the primary cell and the secondary cell for data for a radio link control layer. According to the flow control, the data for the radio link control layer is communicated between the first and second base stations using a link between the first and second base stations. Flow control may be performed between the primary cell and the secondary cell by dynamically controlling a depth of queued radio link control data in the secondary cell for one or more UEs based on one or more factors, e.g., current/future loading of secondary cell, peak theoretical throughput for a UE in the secondary cell, and/or a UE's current channel quality information. Apparatus, methods, and computer program products are disclosed.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Inventors: Subramanian S. Iyer, Mark Marsan, Kirk Ingemunson, Apurv Mathur
  • Patent number: 9940302
    Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada