Patents by Inventor Subramanian S. Iyer
Subramanian S. Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240028884Abstract: Present implementations can include a system with a transistor array including a plurality of charge-trap transistors, the charge-trap transistors being operatively coupled with corresponding input nodes, and a neural integrator including a first integrator node and a second integrator node operatively coupled with the transistor array, and generating an output corresponding to a neuron of a neural network system.Type: ApplicationFiled: October 4, 2021Publication date: January 25, 2024Applicant: The Regents of the University of CaliforniaInventors: Steven L. MORAN, Subramanian S. IYER, Zhe WAN, Sudhakar PAMARTI
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Publication number: 20230238476Abstract: Example implementations include a method of mass transfer of display elements, by depositing one or more resist layers between one or more display elements disposed on a photoemitting layer, depositing at least one stress buffer layer between the resist layers, removing the resist layer and at least a portion of the photoemitting layer disposed in contact with the resist layers to form resist layer gaps on a wafer substrate, dicing the wafer substrate at the resist layer gaps to form at least one wafer die, separating the wafer substrate from the display elements by irradiation at corresponding first surfaces of the display elements, removing the stress buffer layers from the wafer die, and bonding the portion of the display elements to a first handler substrate at one or more electrode pads of the portion of the display elements.Type: ApplicationFiled: June 1, 2021Publication date: July 27, 2023Applicant: The Regents of the University of CaliforniaInventors: Subramanian S. IYER, Goutham EZHILARASU
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Publication number: 20230225225Abstract: Example implementations include a method of manufacturing a quantum computing device, by depositing a superconducting electrode layer on at least a portion of a superconducting wafer, forming a plurality of electrode pads on the superconducting electrode layer, depositing an electrode bonding interlayer on the electrode pads, singulating the superconducting wafer into a first superconducting die including a first electrode pad among the plurality and a second superconducting die including a second electrode pad among the plurality, and integrating the first superconducting die with the second superconducting die at a bonding interface between the first electrode pad and the second electrode pad.Type: ApplicationFiled: May 27, 2021Publication date: July 13, 2023Applicant: The Regents of the University of CaliforniaInventors: Yu-Tao YANG, Subramanian S. IYER
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Patent number: 11538764Abstract: A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.Type: GrantFiled: January 30, 2019Date of Patent: December 27, 2022Assignee: The Regents of the University of CaliforniaInventors: Subramanian S. Iyer, Arsalan Alam, Amir Hanna, Takafumi Fukushima
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Patent number: 11257746Abstract: A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.Type: GrantFiled: November 1, 2018Date of Patent: February 22, 2022Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa
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Patent number: 11239542Abstract: A system is provided for interconnecting multiple functional dies on a single substrate, including: (1) multiple global links in the substrate; (2) multiple local links in the substrate; and (3) multiple utility dies on the substrate, wherein each of the utility dies is connected to at least one of the global links, the utility dies are configured to communicate with one another through the global links, each of the utility dies is connected to at least one of the local links and is configured to communicate with at least one of the functional dies through the at least one of the local links. In some embodiments, an antenna is integrated into the substrate.Type: GrantFiled: September 4, 2020Date of Patent: February 1, 2022Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa, Arpan Dasgupta, Arsalan Alam
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Patent number: 11210373Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: GrantFiled: November 6, 2019Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Publication number: 20210225749Abstract: A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.Type: ApplicationFiled: November 1, 2018Publication date: July 22, 2021Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa
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Publication number: 20210074648Abstract: A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.Type: ApplicationFiled: January 30, 2019Publication date: March 11, 2021Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Subramanian S. IYER, Arsalan ALAM, Amir HANNA, Takafumi FUKUSHIMA
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Patent number: 10930601Abstract: A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.Type: GrantFiled: October 30, 2017Date of Patent: February 23, 2021Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Subramanian S. Iyer, Takafumi Fukushima, Adeel A. Bajwa
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Publication number: 20200406039Abstract: A spinal cord stimulator includes: (1) a flexible substrate; (2) a power source embedded in the flexible substrate; (3) a controller embedded in the flexible substrate and connected to the power source; and (4) an array of electrodes, including an array of stimulation electrodes, disposed over the flexible substrate and connected to the controller, wherein the controller is configured to direct the array of stimulation electrodes to deliver a stimulation pattern to a spinal cord of a patient.Type: ApplicationFiled: March 15, 2019Publication date: December 31, 2020Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Bilwaj Gaonkar, Steven L. Moran, Amir Hanna, Luke Macyszyn, Subramanian S. Iyer
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Publication number: 20200403293Abstract: A system is provided for interconnecting multiple functional dies on a single substrate, including: (1) multiple global links in the substrate; (2) multiple local links in the substrate; and (3) multiple utility dies on the substrate, wherein each of the utility dies is connected to at least one of the global links, the utility dies are configured to communicate with one another through the global links, each of the utility dies is connected to at least one of the local links and is configured to communicate with at least one of the functional dies through the at least one of the local links. In some embodiments, an antenna is integrated into the substrate.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa, Arpan Dasgupta, Arsalan Alam
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Patent number: 10740282Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.Type: GrantFiled: February 26, 2018Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Patent number: 10657231Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: GrantFiled: January 3, 2019Date of Patent: May 19, 2020Assignee: International Business Machines CorporationInventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Patent number: 10613754Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: GrantFiled: October 9, 2019Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Fine-grained analog memory device based on charge-trapping in high-K gate dielectrics of transistors
Patent number: 10585643Abstract: A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.Type: GrantFiled: May 15, 2017Date of Patent: March 10, 2020Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Xuefeng Gu, Subramanian S. Iyer -
Publication number: 20200074051Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Publication number: 20200042182Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: ApplicationFiled: October 9, 2019Publication date: February 6, 2020Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Patent number: 10503402Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: GrantFiled: December 27, 2017Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Publication number: 20190287927Abstract: A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.Type: ApplicationFiled: October 30, 2017Publication date: September 19, 2019Inventors: Subramanian S. IYER, Takafumi FUKUSHIMA, Adeel A. BAJWA