Patents by Inventor Subramanian S. Iyer
Subramanian S. Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10342060Abstract: In a communication system where a primary cell is controlled by a first base station and a secondary cell is controlled by a second, different base station, flow control is performed between the primary cell and the secondary cell for data for a radio link control layer. According to the flow control, the data for the radio link control layer is communicated between the first and second base stations using a link between the first and second base stations. Flow control may be performed between the primary cell and the secondary cell by dynamically controlling a depth of queued radio link control data in the secondary cell for one or more UEs based on one or more factors, e.g., current/future loading of secondary cell, peak theoretical throughput for a UE in the secondary cell, and/or a UE's current channel quality information. Apparatus, methods, and computer program products are disclosed.Type: GrantFiled: December 27, 2017Date of Patent: July 2, 2019Assignee: Nokia Solutions and Networks OyInventors: Subramanian S. Iyer, Mark Marsan, Kirk Ingemunson, Apurv Mathur
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Publication number: 20190155999Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: ApplicationFiled: January 3, 2019Publication date: May 23, 2019Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Patent number: 10262119Abstract: An authenticating service of a chip having an intrinsic identifier (ID) is provided. The authenticating device includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: GrantFiled: April 17, 2017Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Publication number: 20180189233Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.Type: ApplicationFiled: February 26, 2018Publication date: July 5, 2018Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arhur, John E. Barth, JR., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Publication number: 20180136846Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: ApplicationFiled: December 27, 2017Publication date: May 17, 2018Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Publication number: 20180124851Abstract: In a communication system where a primary cell is controlled by a first base station and a secondary cell is controlled by a second, different base station, flow control is performed between the primary cell and the secondary cell for data for a radio link control layer. According to the flow control, the data for the radio link control layer is communicated between the first and second base stations using a link between the first and second base stations. Flow control may be performed between the primary cell and the secondary cell by dynamically controlling a depth of queued radio link control data in the secondary cell for one or more UEs based on one or more factors, e.g., current/future loading of secondary cell, peak theoretical throughput for a UE in the secondary cell, and/or a UE's current channel quality information. Apparatus, methods, and computer program products are disclosed.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Inventors: Subramanian S. Iyer, Mark Marsan, Kirk Ingemunson, Apurv Mathur
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Patent number: 9940302Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.Type: GrantFiled: April 19, 2016Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Patent number: 9886193Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: GrantFiled: May 15, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Patent number: 9888513Abstract: In a communication system where a primary cell is controlled by a first base station and a secondary cell is controlled by a second, different base station, flow control is performed between the primary cell and the secondary cell for data for a radio link control layer. According to the flow control, the data for the radio link control layer is communicated between the first and second base stations using a link between the first and second base stations. Flow control may be performed between the primary cell and the secondary cell by dynamically controlling a depth of queued radio link control data in the secondary cell for one or more UEs based on one or more factors, e.g., current/future loading of secondary cell, peak theoretical throughput for a UE in the secondary cell, and/or a UE's current channel quality information. Apparatus, methods, and computer program products are disclosed.Type: GrantFiled: June 8, 2015Date of Patent: February 6, 2018Assignee: Nokia Solutions and Networks OyInventors: Subramanian S. Iyer, Mark Marsan, Kirk Ingemunson, Apurv Mathur
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FINE-GRAINED ANALOG MEMORY DEVICE BASED ON CHARGE-TRAPPING IN HIGH-K GATE DIELECTRICS OF TRANSISTORS
Publication number: 20170329575Abstract: A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.Type: ApplicationFiled: May 15, 2017Publication date: November 16, 2017Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Xuefeng Gu, Subramanian S. Iyer -
Patent number: 9792251Abstract: Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.Type: GrantFiled: January 6, 2017Date of Patent: October 17, 2017Assignee: International Business Machines CorporationInventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Patent number: 9748114Abstract: A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.Type: GrantFiled: February 26, 2015Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Subramanian S. Iyer, Pranita Kerber, Ali Khakifirooz
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Publication number: 20170220784Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Patent number: 9690927Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.Type: GrantFiled: March 16, 2015Date of Patent: June 27, 2017Assignee: International Business Machines CorporationInventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
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Publication number: 20170124024Abstract: Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.Type: ApplicationFiled: January 6, 2017Publication date: May 4, 2017Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, JR., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Patent number: 9588937Abstract: Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.Type: GrantFiled: February 28, 2013Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
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Patent number: 9543229Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: GrantFiled: December 27, 2013Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Patent number: 9536809Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: GrantFiled: August 30, 2015Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Publication number: 20160334991Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Patent number: 9466538Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together.Type: GrantFiled: November 25, 2015Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Spyridon Skordas, Subramanian S Iyer, Donald Francis Canaperi, Shidong Li, Wei Lin