Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

Abstract: Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.

Abstract: A hybrid plasmonic waveguide and associated methods are disclosed. In one example, the electronic device includes combining an electromagnetic wave propagating in a waveguide with a high refractive index and a surface plasmon from a metal surface to create a hybrid plasmon wave in a low refractive index material separating the dielectric waveguide and metal surface. In selected examples, surface mounted hybrid plasmonic waveguides are shown. In selected examples hybrid plasmonic waveguides embedded in glass interposers are shown.

Abstract: Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.

Abstract: Through-glass vias (TGVs) are formed without the use of a planarization step to planarize the TGV fill material after filling holes that extend through a glass layer with the fill material. After the holes are filled with the fill material, the fill material is etched and the glass layer is etched. After etching of the glass is performed, the top and bottom surfaces of the glass layer are recessed relative to the top and bottom surfaces of the fill material in the holes, resulting in formation of fill material stubs. TGV pads are then formed on the fill material stubs. The resulting pads can have protrusions that extend away from a surface of the glass layer. If the TGVs are plated through-holes, a portion of the metal lining the inner wall of a TGV hole can extend past a surface of the glass layer and into a TGV pad.

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes for improving the refractive index of the coating that optically couples with an optical medium, wherein the coating includes one or more layers that include a plurality of nanorods. The plurality of nanorods within each of the one or more layers may have a similar orientation in the chemical composition. The nanorods within separate layers may have different characteristics, including different orientations, different sizes, and/or different chemical compositions. Other embodiments may be described and/or claimed.

Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

Abstract: Embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a PIC. In embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the PIC and the optical waveguide. In embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the PIC interacts with in a Plasmon effect to focus the light on to the optical waveguide. Other embodiments may be described and/or claimed.

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

Abstract: An apparatus is provided which comprises: an interposer comprising glass, one or more redistribution layers on a first interposer surface, one or more conductive contacts on a second interposer surface opposite the first interposer surface, one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the redistribution layers on the first interposer surface, an integrated circuit device embedded within a cavity in the interposer between the first and second interposer surfaces, the embedded integrated circuit device coupled with a first redistribution layers surface, a stack of two or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface, and mold material surrounding at least one side of the stack of two or more integrated circuit devices. Other embodiments are also disclosed and claimed.

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface and an opposing second surface; a conductive via coupled to the first surface of the conductive pad; a microelectronic component having a conductive contact, the conductive contact of the microelectronic component electrically coupled, by an interconnect, to the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin; and a liner between the interconnect and the second surface of the conductive pad, and wherein a material of the liner includes nickel, palladium, or gold. In some embodiments, a bottom surface of the liner is curved outward towards the conductive pad. In some embodiments, the liner also may be on side surfaces of the interconnect.

Abstract: Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.