Abstract: Substrates with nitrided glass cores, and methods of forming the same, are described herein. In one example, a substrate includes one or more glass layers and a plurality of dielectric layers. At least one of the glass layers includes nitrogen. Further, at least one of the dielectric layers is above the one or more glass layers and at least one of the dielectric layers is below the one or more glass layers.

Abstract: High-density IC die package routing structures with one or more nitrided surfaces. Metallization features may be formed, for example with a plating process. Following the plating process, a surface of the metallization features may be exposed to a surface treatment that incorporates nitrogen onto a surface of the metallization. The presence of nitrogen may chemically improve adhesion between finely patterned metallization features and package dielectric material. Accordingly, surface roughness of metallization features may be reduced without suffering delamination. With lower surface roughness, metallization features may transmit higher frequency data signals with lower insertion loss.

Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example package assembly includes a substrate, a dielectric layer and a conductive layer between the substrate and the dielectric layer. The conductive layer has a surface roughness of less than 1 micrometer (?m). A film is provided between the dielectric layer and the conductive layer, and between exposed surfaces of the substrate adjacent the conductive layer and the dielectric layer. The film including silicon and nitrogen and being substantially free of hydrogen.

Abstract: Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same. The microelectronics packages may include a core material, a first plurality of pads, and a silicon nitride layer. The first plurality of pads are attached to the core material. The silicon nitride layer is attached to the core material. The silicon nitride material defines respective openings to expose at least a portion of each of the first plurality of pads.

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an organic adhesion promoter layer on the surface of a copper trace to reduce delamination between a dielectric material and the surface of the copper trace, and to facilitate a smooth surface interface between the surface of the copper trace and of a copper feature, such as a copper-filled via, placed on the surface of the copper trace. The smooth surface interface reduces insertion loss and enables routing of higher frequency signals on a package, and does not require roughing of the copper trace in order to adhere to the dielectric material. Other embodiments may be described and/or claimed.

Abstract: An electronic device package comprises a conductive feature over a first surface of a package substrate, the conductive feature to couple to an integrated circuit die; a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen; a second dielectric layer over the first dielectric layer and having a second thickness different than the first thickness and comprising silicon and nitrogen; and a third dielectric layer over the second dielectric layer and comprising an organic material.

Abstract: Various embodiments disclosed relate to a semiconductor assembly interconnect structure. The present disclosure includes an interconnect structure that case include a substrate, a metallic layer thereon, an adhesion promoter film formed over the metallic layer and forming a flat region over a flat portion of the metallic layer, a solder resist layer formed over the adhesion promoter film, an opening in the solder resist layer and the adhesion promoter film in the flat region of the adhesion promotion film, the opening connecting to the flat portion of the metallic layer, and a stacked electrical connector formed on the metallic layer within the opening.

Abstract: An electronic device package comprises a substrate with a first side and a second side opposite the first side; a first conductive feature on the first side and having a first surface; a first dielectric material in contact with the first surface, wherein the first dielectric material has a first composition comprising silicon and nitrogen; a second conductive feature on the second side of the substrate and having a second surface; and a second dielectric material in contact with the second surface, wherein the second dielectric material has a second composition different than the first composition, and wherein a surface roughness of the second surface is greater than a surface roughness of the first surface.

Abstract: An electronic device comprises a substrate layer comprising a first side and an opposing second side, a through hole passing through the substrate layer between the first side and the second side, a first electrical pathway passing from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer, a second electrical pathway passing from a second position on the first side of the substrate layer, through a second portion of the through hole, to a corresponding second position on the second side of the substrate layer, and an insulation layer between the first electrical pathway and the second electrical pathway within the through hole, wherein the insulation layer electrically isolates the first electrical pathway from the second electrical pathway.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.

Abstract: Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

Abstract: Methods, apparatus, systems, and articles of manufacture to improve signal integrity performance in integrated circuit packages are disclosed. An integrated circuit (IC) package includes a substrate; a first conductive pad in a first metal layer in the substrate; and a second conductive pad in a second metal layer in the substrate. The first metal layer is adjacent the second metal layer with no intervening metal layers therebetween. The integrated circuit (IC) package further includes a conductive protrusion extending from the first conductive pad toward the second conductive pad.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon, nitrogen, and a catalyst, and where the second layer is chemically bonded to one of the first layers.

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate, and a second layer is over the trace, where the second layer comprises silicon and nitrogen.