Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

Abstract: Techniques for a glass core inductor are disclosed. In the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (FIVR). The FIVR includes a glass core inductor that is embedded in the glass substrate. Each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. The inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.

Abstract: In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.

Abstract: A microelectronic structure, a semiconductor package including the structure, an IC device assembly including the structure, and a method of making the structure. The microelectronic structure includes: a first buildup layer and a second buildup layer including respective first and second electrically conductive structures; and a bridge layer including a glass material extending across a width thereof, the bridge layer between the first buildup layer and the second buildup layer and comprising: an interconnect bridge including third electrically conductive structures coupling a first set of the first electrically conductive structures to a second set of the first electrically conductive structures. Through glass vias (TGVs) extending from a top surface to a bottom surface of the bridge layer, the TGVs coupling a third set of the first electrically conductive structures to at least some of the second electrically conductive structures.

Abstract: A glass core with a cavity-less local interconnect component architecture for complex multi-die packages. The apparatus has the local interconnect component attached directly to a planar glass layer and surrounded by mold. One or more redistribution layers may be located above and below the apparatus.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

Abstract: Embodiments of a microelectronic assembly comprise: a first layer comprising a plurality of first integrated circuit (IC) dies in an organic dielectric material, the first layer having a first side and a second side opposite to the first side; a second layer on the first side of the first layer, the second layer comprising a second IC die in the organic dielectric material, the second IC die conductively coupling a pair of first IC dies in the plurality of first IC dies of the first layer; and a package substrate coupled to the second side of the first layer. The second IC die is coupled to the pair of first IC dies by interconnects having a pitch less than 60 micrometers between adjacent interconnects, and the pair of first IC dies comprises TSVs conductively coupling circuits in the first IC dies with the interconnects.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.

Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.