Patents by Inventor Sudhanshu Misra

Sudhanshu Misra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6287970
    Abstract: A method of making a semiconductor device includes the steps of forming an oxide layer adjacent a semiconductor substrate, etching trenches within the oxide layer, depositing a copper layer to at least fill the etched trenches, and forming a copper arsenate layer on the deposited copper layer. The copper arsenate layer is then chemically mechanically polished. The copper layer may be deposited by at least one of electrodeposition, electroplating and chemical vapor deposition. The copper arsenate layer on the surface of the deposited copper layer inhibits oxidation and corrosion and stabilizes the microstructure of the deposited copper layer to thereby eliminate a need to subsequently anneal the deposited copper layer.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: September 11, 2001
    Assignee: Agere Systems Inc.
    Inventors: Sailesh Mansinh Merchant, Sudhanshu Misra, William Michael Moller, Pradip Kumar Roy
  • Patent number: 6274429
    Abstract: An oxidation process for reducing the data retention loss (DRL) in a FAMOS device comprising the steps of (1) low temperature deposition of a silicon-enriched silicon oxide (130) over a FAMOS transistor gate stack (116) and (2) annealing said silicon-enriched oxide (130) at a high temperature in oxygen atmosphere to convert said silicon-enriched oxide (130) to a thermal oxide. The silicon enriched oxide (130) acts as both an oxygen getter and diffusion barrier during the annealing step.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: August 14, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Sudhanshu Misra
  • Patent number: 6258231
    Abstract: An apparatus for determining the endpoint in a chemical mechanical polishing operation used for polishing a metal-containing material includes an electrochemical cell and an electronic circuit. An acidic polishing slurry is used to oxidize the metal and the oxidized metal is included in an effluent slurry stream, a sample of which is provided to the apparatus. The apparatus includes a liquid-phase working electrode, a reference electrode and a solid electrolyte which allows for the interchange of ions between the electrodes. An electronic circuit is coupled to the electrode for monitoring the component activity of the effluent slurry stream by measuring the electric potential across the electrodes. When the measured electric potential changes, indicating a change in the composition of the effluent slurry, endpoint is indicated.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: July 10, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: William Graham Easter, Sudhanshu Misra, Pradip Kumar Roy, Susan Clay Vitkavage
  • Patent number: 6214732
    Abstract: A method for determining the endpoint in a chemical mechanical polishing operation used for polishing a metal-containing material. An acidic polishing slurry is used to oxidize the metal and the oxidized metal is included in an effluent slurry stream. The effluent slurry stream is directed into a vessel which forms an electrochemical cell. The component activity of the effluent slurry stream is monitored within the electrochemical cell by measuring the electric potential across the electrodes of the electrochemical cell. When the measured electric potential changes, indicating a change in the composition of the effluent slurry, endpoint is indicated.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: April 10, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: William Graham Easter, Sudhanshu Misra, Pradip Kumar Roy, Susan Clay Vitkavage
  • Patent number: 6130150
    Abstract: A method of making a semiconductor device includes forming at least one opening, having vertical sidewalls and a bottom, in a first dielectric layer adjacent a substrate. A second dielectric layer is formed to line the vertical sidewalls of the at least one opening, and has a relatively lower etch rate than the first dielectric layer. A conductive layer is deposited to fill the at least one opening and an upper surface of the semiconductor wafer is cleaned. The method preferably includes the steps of depositing a barrier layer lining the second dielectric layer and the bottom of the at least one opening, and chemically mechanically polishing the semiconductor wafer with the second dielectric layer protecting upper edges of the barrier layer and conductive layer.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: October 10, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Sailesh Mansinh Merchant, Sudhanshu Misra, Pradip Kumar Roy
  • Patent number: 6114234
    Abstract: A method of making a semiconductor with a passivating film for copper interconnects includes the step of etching a first set of trench openings within a second oxide layer and then through an etch stop layer that has been deposited over a first oxide layer on a semiconductor substrate. At least a second set of openings are etched in the first oxide layer within the bounds defined by each of a first set of openings. A copper layer is deposited and a passivating film formed on top of the deposited copper layer by depositing one of either a chromate or chromite on the deposited copper layer and forming a respective copper chromate or copper chromite composition. The passivating film is chemically mechanically polished with a slurry containing a respective nitric acid when the passivating film is formed from a chromite and ammonium hydroxide when the passivating film is formed from a chromate.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: September 5, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Sailesh M. Merchant, Sudhanshu Misra, Pradip K. Roy
  • Patent number: 6100587
    Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: August 8, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Sailesh Mansinh Merchant, Sudhanshu Misra, Pradip Kumar Roy
  • Patent number: 6071808
    Abstract: A method of passivating copper interconnects is disclosed. A freshly electrodeposited copper interconnect such as formed as via/trench structures in semiconductor manufacturing is chemically converted to passivating surface of copper tungstate or copper chromate either through MOCVD reaction with vapors of tungsten or chromium alkoxides, or by pyrolytic reaction with tungsten or chromium carbonyl in the presence of O.sub.2. The copper interconnect having the formed passivation service is then chemically mechanically polished. The process can be used with various manufacturing processes, including single and dual damascene processes.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: June 6, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Sailesh M. Merchant, Sudhanshu Misra, Pradip K. Roy