Abstract: The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads.

Abstract: Described herein are polishing apparatus, polishing formulations, and polymeric substrates for use in polishing surfaces, and related methods. The apparatus, formulations, substrates, and methods may each be used in applications involving the polishing of metal and/or metal-containing surfaces such as semiconductor wafers. The apparatus, formulations, polymeric substrates, and related methods described herein may be used without abrasives, and in some instances, without mechanical friction of a pad surface against the surface to be polished. Therefore, defects on a polished surface due to such mechanical polishing processes may be reduced.

Abstract: CMP pads having novel groove configurations are described. For example, described herein are CMP pads comprising primary grooves, secondary grooves, a groove pattern center, and an optional terminal groove. The CMP pads may be made from polyurethane or poly (urethane-urea), and the grooves produced therein may be made by a method from the group consisting of molding, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

Abstract: The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads.

Abstract: A polishing pad for chemical mechanical planarization of a film on a substrate is customized by obtaining one or more characteristics of a structure on a substrate. For example, when the structure is a chip formed on a semiconductor wafer, the one or more characteristics of the structure can include chip size, pattern density, chip architecture, film material, film topography, and the like. Based on the one or more characteristics of the structure, a value for the one or more chemical or physical properties of the pad is selected. For example, the one or more chemical or physical properties of the pad can include pad material hardness, thickness, surface grooving, pore size, porosity, Youngs modulus, compressibility, asperity, and the like.

Abstract: The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads.

Abstract: A polishing pad for chemical mechanical planarization of a film on a substrate is customized by obtaining one or more characteristics of a structure on a substrate. For example, when the structure is a chip formed on a semiconductor wafer, the one or more characteristics of the structure can include chip size, pattern density, chip architecture, film material, film topography, and the like. Based on the one or more characteristics of the structure, a value for the one or more chemical or physical properties of the pad is selected. For example, the one or more chemical or physical properties of the pad can include pad material hardness, thickness, surface grooving, pore size, porosity, Youngs modulus, compressibility, asperity, and the like.

Abstract: The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior themo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads.

Abstract: Various examples of customized polishing pads are given, along with methods of making and using such customized polishing pads. The subject customized pads are designed and fabricated so that there is spatial distribution of chemical and physical properties of the pads that are customized for performance suited to a specific type of substrate, as well as fabrication control in implementing such customized design. Such customized design and fabrication control produce a monolithic pad thereby specifically suited to provide uniform performance of CMP of the targeted substrate.

Abstract: A polishing pad for chemical mechanical planarization of a film on a substrate is customized by obtaining one or more characteristics of a structure on a substrate. For example, when the structure is a chip formed on a semiconductor wafer, the one or more characteristics of the structure can include chip size, pattern density, chip architecture, film material, film topography, and the like. Based on the one or more characteristics of the structure, a value for the one or more chemical or physical properties of the pad is selected. For example, the one or more chemical or physical properties of the pad can include pad material hardness, thickness, surface grooving, pore size, porosity, Youngs modulus, compressibility, asperity, and the like.

Abstract: A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout regions overlying the semiconductor substrate. Each layout region will comprise an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacturing. Each dummy fill region in each layout region will have a different density with respect to other dummy fill regions in other layout regions, so that the combined density of the active interconnect feature region and the dummy fill feature region in a layout region will be substantially uniform with respect to a similar combined density in each of the other layout regions.

Abstract: An improved polishing pad (22) for use in a chemical mechanical polishing (CMP) operation as part of a semiconductor device fabrication process. The polishing pad is formed of a plurality of particles of abrasive material (24) disposed in a matrix material (26). The abrasive particles may be a stiff inorganic material coated with a coupling agent, and the matrix material may be a polymeric material such as polyurethane. As the polishing pad wears through repeated polishing operations, the newly exposed polishing surface will contain fresh abrasive particles and will exhibit the same polishing properties as the original surface, thereby providing consistent polishing performance throughout the life of the pad without the need for conditioning operations. In one embodiment the distribution of particles of abrasive material per unit volume of matrix material may vary from one portion (23) of the pad to another (25).

Abstract: Tantalum and niobium aluminum-doped hydrated mixed metal oxide sols may be made by a process comprising combining a first metal compound aluminum alkoxide, with a second metal compound selected from the group consisting of niobium alkoxide and tantalum alkoxide, and mixtures thereof to provide a substantially water-free precursor and combining the precursor with a ketone to provide a hydrated mixed metal oxide sol, wherein the ketone is substantially free of water. The sol may then be processed to obtain thin films, fibers, crystals (both micro- and meso-porous), powders and macroscopic objects and to provide mixed metal oxide that may be used in a variety of components of integrated circuits.

Abstract: The present invention provides a chemical mechanical planarization (CMP) polishing composition that polishes metal layers at a good removal rate and that provides good planarization of metal layers in a process that can be readily controlled. The CMP polishing composition of the present composition includes a plurality of abrasive particles, a triazole or a triazole derivative, a ferricyanide salt oxidizing agent and water and has a pH of from about 1 to about 6. In addition, the present invention includes a method for removing at least a portion of a metallization layer by polishing a metallization layer using the CMP polishing composition of the invention.

Abstract: The present invention provides a method of manufacturing an integrated circuit including planarizing a semiconductor wafer surface. In one embodiment, the method comprises forming a dielectric layer over a first level having an irregular topography, depositing a sacrificial material over the dielectric layer, and then planarizing the semiconductor wafer surface to a planar surface. More specifically, the dielectric layer forms such that it substantially conforms to the irregular topography of the first level. The sacrificial material is formed to a substantially planar surface over the dielectric layer. Thus, the sacrificial material provides a substantially uniform chemical/mechanical planarization (CMP) process removal rate across the semiconductor wafer surface. In the ensuing step, planarizing the semiconductor wafer surface to a planar surface removes the sacrificial material and a portion of the dielectric layer with a CMP process.

Abstract: The present invention provides a composite polishing pad, comprising. In an advantageous embodiment, the composite polishing pad includes a polishing pad member comprising a material having a predetermined hardness and an annular support member underlying a periphery of the polishing pad member, the annular support member having a hardness less than the predetermined hardness of the polishing pad member.

Abstract: Tantalum and niobium aluminate mixed metal oxides may be made by a process comprising mixing a first metal compound selected from the group consisting of aluminum alkoxide, aluminum beta-diketonate, aluminum alkoxide beta-diketonate, and mixtures thereof with a second metal compound selected from the group consisting of niobium alkoxide, niobium beta-diketonate, niobium alkoxide beta-diketonate, tantalum alkoxide, tantalum beta-diketonate, tantalum alkoxide beta-diketonate, and mixtures thereof to provide a precursor and then hydrolyzing the mixture. The resulting mixed metal oxide may be used in a variety of components of integrated circuits.

Abstract: An improved polishing pad (22) for use in a chemical mechanical polishing (CMP) operation as part of a semiconductor device fabrication process. The polishing pad is formed of a plurality of particles of abrasive material (24) disposed in a matrix material (26). The abrasive particles may be a stiff inorganic material coated with a coupling agent, and the matrix material may be a polymeric material such as polyurethane. As the polishing pad wears through repeated polishing operations, the newly exposed polishing surface will contain fresh abrasive particles and will exhibit the same polishing properties as the original surface, thereby providing consistent polishing performance throughout the life of the pad without the need for conditioning operations. In one embodiment the distribution of particles of abrasive material per unit volume of matrix material may vary from one portion (23) of the pad to another (25).

Abstract: A method an apparatus for making copper metallic interconnects for semiconductors having an oxide layer deposited in the copper in situ during the deposition of the copper within the via.

Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desired density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.