Abstract: A method of maintaining a power supply voltage during a brownout is disclosed. The method includes the step of storing a charge in a charge reservoir (608) and storing a charge on a power supply capacitor (832). A charge from the charge reservoir is applied to the power supply capacitor in response to a power supply fail signal (BROWNOUT).

Abstract: A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit (700) is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.

Abstract: A method of reading a memory cell. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first bitline is charged to a reference voltage (VREF) from the reference voltage generator. The reference voltage generator is disconnected (RFWL_A/B low at t4, FIG. 10B) from the first bitline. A signal voltage (PL high at t4, FIG. 10B) from the memory cell is applied to a second bitline (BL) after the step of disconnecting. A difference voltage between the first and second bitlines is amplified (SAEN high at t7, FIGS. 8A and 10B).

Abstract: A method of maintaining a power supply voltage during a brownout is disclosed. The method includes the step of storing a charge in a charge reservoir (608) and storing a charge on a power supply capacitor (832). A charge from the charge reservoir is applied to the power supply capacitor in response to a power supply fail signal (BROWNOUT).

Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

Abstract: A method of reading a memory cell is disclosed. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first bitline is charged to a reference voltage (VREF) from the reference voltage generator. The reference voltage generator is disconnected (RFWL_A/B low at t4, FIG. 10B) from the first bitline. A signal voltage (PL high at t4, FIG. 10B) from the memory cell is applied to a second bitline (BL) after the step of disconnecting. A difference voltage between the first and second bitlines is amplified (SAEN high at t7, FIGS. 8A and 10B).

Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Abstract: A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers.

Abstract: An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.

Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.

Abstract: A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers.

Abstract: One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.

Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.

Abstract: One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.

Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).