Abstract: A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) is coupled to a respective column of memory cells in each first part. A second conductor (752) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row.

Abstract: An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.

Abstract: A method of forming a memory circuit comprising six transistor memory cells. The memory cells comprise first and second inverters. The inverters comprise respective first and second drive transistors and first and second pull-up transistors. The method also forms a plurality of conducting plugs. A first conducting plug is coupled to the first inverter and a second conducting plug is coupled to the first pull-up transistor and to the gates of the second drive transistor and the second pull-up transistor. A third conducting plug is coupled to the second inverter and a fourth conducting plug coupled to the second pull-up transistor and to the gates of the first drive transistor and the first pull-up transistor. The method also forms conducting elements. A first conducting element contacts the first conducting plug and the second conducting plug and a second conducting element contacts the third conducting plug and the fourth conducting plug.

Abstract: A memory circuit and method to improve signal margin is disclosed. The circuit includes a memory array arranged in rows 702, 704, 706 and columns 750, 752 of memory cells. Each row of memory cells is connected to a respective wordline. Each column of memory cells is connected to one of a bitline and a complementary bitline. An active wordline accesses a respective row of memory cells. The memory circuit includes a plurality of precharge circuits 724, 726, 728. Each precharge circuit is connected to a respective column of memory cells and coupled to receive a precharge signal PRE. An active precharge signal renders a respective precharge circuit conductive. A control and decode circuit 700 changes an inactive wordline signal to an active wordline signal while the precharge signal is active.

Abstract: Apparatus and methods are provided for providing reference voltages during read operations in ferroelectric memories, in which a bitline of a reference array substantially similar or identical to a portion of a ferroelectric data array is precharged and then coupled with a bitline in the data array to provide a reference voltage according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.

Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first 106 and a second 110 control terminal and a pass transistor 102. The pass transistor has a control gate coupled to the first control terminal. The memory circuit includes a drive circuit 900 having an output terminal 912 coupled to the second control terminal. The drive circuit is arranged to produce a control signal PL having a rise time and a fall time, wherein the fall time is greater than the rise time.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: Apparatus and methods are provided for providing reference voltages during read operations in ferroelectric memories, in which a bitline of a reference array substantially similar or identical to a portion of a ferroelectric data array is precharged and then coupled with a bitline in the data array to provide a reference voltage according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.

Abstract: Methods and apparatus are disclosed for selectively coupling sense amps with local IO lines in memory devices, comprising first and second selection systems operable to selectively couple a sense amp terminal with a local IO line. A first selection system is coupled with a local IO line and a sense amp, providing selective coupling thereof a second time period after the sense amp is enabled. A second selection system is coupled with the local IO line and the sense amp, which couples the local IO line with the sense amp a first time period before the sense amp is enabled during a write operation, wherein the first time period may be zero.

Abstract: Methods are disclosed for reading data from memory cells such as a ferroelectric memory cell in a memory device, where one sense amp bitline is coupled with a precharge voltage while another sense amp bitline is coupled with the memory cell.

Abstract: Methods and apparatus are disclosed for selectively coupling sense amps with local IO lines in memory devices, comprising first and second selection systems operable to selectively couple a sense amp terminal with a local IO line. A first selection system is coupled with a local IO line and a sense amp, providing selective coupling thereof a second time period after the sense amp is enabled. A second selection system is coupled with the local IO line and the sense amp, which couples the local IO line with the sense amp a first time period before the sense amp is enabled during a write operation, wherein the first time period may be zero.

Abstract: Methods and apparatus are disclosed for reading data from memory cells such as a ferroelectric memory cell in a memory device, where one sense amp bitline is coupled with a precharge voltage while another sense amp bitline is coupled with the memory cell.

Abstract: According to one embodiment of the present invention, a semiconductor structure includes an SOI memory cell having a pass transistor having a body and a driver transistor having a body. The SOI memory cell also includes a source voltage contact coupling the bodies of the pass transistor and the driver transistor and a non-square conductive active region coupled to the source voltage contact. The shortest distance between the body of the pass transistor and the source voltage contact is greater than the shortest distance between the body of the pass transistor and the body of the driver transistor, and the shortest distance between the body of the pass transistor and the non-square conductive active region is less than the shortest distance between the bodies of the pass transistor and the driver transistor.

Abstract: According to one embodiment of the present invention, a semiconductor structure includes an SOI memory cell having a pass transistor having a body and a driver transistor having a body. The SOI memory cell also includes a source voltage contact coupling the bodies of the pass transistor and the driver transistor and a non-square conductive active region coupled to the source voltage contact. The shortest distance between the body of the pass transistor and the source voltage contact is greater than the shortest distance between the body of the pass transistor and the body of the driver transistor, and the shortest distance between the body of the pass transistor and the non-square conductive active region is less than the shortest distance between the bodies of the pass transistor and the driver transistor.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: To provide a conducting path between the metal—0 layer and a metal—1 interconnect layer, two layers with conducting plugs were necessary in the prior art. In the present invention, the conducting regions electrically coupling two regions of the integrated circuit are formed at the same time as the formation of the conducting plugs coupling selected portions of the integrated circuit with the metal—1 interconnect layer. The conducting regions, as with the conducting plugs, extend to surface of the insulating layer upon which the metal—1 interconnect paths are patterned. Using this technique, process steps required in the prior art can be eliminated. This process has the limitation that the metal—1 interconnect layer can not be formed over the conducting regions.

Abstract: To provide a conducting path between the metal_0 layer and a metal_1 interconnect layer, two layers with conducting plugs were necessary in the prior art. In the present invention, the conducting regions electrically coupling two regions of the integrated circuit are formed at the same time as the formation of the conducting plugs coupling selected portions of the integrated circuit with the metal_1 interconnect layer. The conducting regions, as with the conducting plugs, extend to surface of the insulating layer upon which the metal_1 interconnect paths are patterned. Using this technique, process steps required in the prior art can be eliminated. This process has the limitation that the metal_1 interconnect layer can not be formed over the conducting regions.

Abstract: An integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. In one embodiment the strapping 750, 752, 756 is placed between the moats 706,724 of transistors that compose cross-coupled inverters within a static random access memory cell.

Abstract: A static random access memory array (200) with power supplies and an array biasing scheme is disclosed. A power supply (202) has an output voltage that is applied to the bitlines (40). The output voltage pre-charges the bitlines (40) to read from the memory cells (10). An array power supply (204) has an array voltage that is applied to the memory cells. The array voltage is higher than the output voltage. The array power supply (204) is drived by boosting the output voltage of the power supply (202).

Abstract: A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first inverter (12) and a first bitline (36). A first write pass transistor (32) is placed in parallel with the first pass transistor (24). A series combination of a second pass transistor (26) and a second bitline select transistor (30) is connected between an output node (17) of the second inverter (18) and a second bitline (38). A second write pass transistor (34) is placed in parallel with the second pass transistor (26).