Abstract: A method of forming a microelectronic device is described comprising the steps of providing a substrate, forming a conductive region on the substrate, and forming an insulating layer on said conductive region and said substrate. The method further comprises the steps of forming a spacer layer on said insulating layer, removing selective portions of said spacer layer and said insulating layer to expose a selective area of said conductive region thereby forming a storage node contact window, and forming a first conductive layer on said spacer layer and within said storage node contact window wherein said first conductive layer is in electrical communication with said conductive region.

Abstract: A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first inverter (12) and a first bitline (36). A first write pass transistor (32) is placed in parallel with the first pass transistor (24). A series combination of a second pass transistor (26) and a second bitline select transistor (30) is connected between an output node (17) of the second inverter (18) and a second bitline (38). A second write pass transistor (34) is placed in parallel with the second pass transistor (26).

Abstract: A method of forming an integrated circuit capacitor is disclosed comprising the steps of providing a substrate, forming a conductive region at the substrate, and forming an insulating layer on the conductive region and the substrate. The method further comprises the steps of removing selective portions of the insulating layer to expose a selective area of the conductive region thereby forming a storage node contact window and forming a first conductive layer on the insulating layer and within the storage node contact window wherein the first conductive layer is in electrical communication with the conductive region. Next a cavity is formed in the first conductive layer. Subsequently, selected portions of the first conductive layer are removed leaving at least a remaining portion of the first conductive layer in which the cavity is formed thereby isolating the remaining portion of the first conductive layer from surrounding circuit elements.

Abstract: A method of forming a microelectronic device is described comprising the steps of providing a substrate, forming a conductive region on the substrate, and forming an insulating layer on said conductive region and said substrate. The method further comprises the steps of forming a spacer layer on said insulating layer, removing selective portions of said spacer layer and said insulating layer to expose a selective area of said conductive region thereby forming a storage node contact window, and forming a first conductive layer on said spacer layer and within said storage node contact window wherein said first conductive layer is in electrical communication with said conductive region.

Abstract: A method of forming an integrated circuit capacitor is disclosed comprising the steps of providing a substrate, forming a conductive region at the substrate, and forming an insulating layer on the conductive region and the substrate. The method further comprises the steps of removing selective portions of the insulating layer to expose a selective area of the conductive region thereby forming a storage node contact window and forming a first conductive layer on the insulating layer and within the storage node contact window wherein the first conductive layer is in electrical communication with the conductive region. Next a cavity is formed in the first conductive layer. Subsequently, selected portions of the first conductive layer are removed leaving at least a remaining portion of the first conductive layer in which the cavity is formed thereby isolating the remaining portion of the first conductive layer from surrounding circuit elements.

Abstract: A method for forming a storage capacitor (12) including the step of forming a storage node contact window (38) and forming a cavity (48) in the storage electrode (50) such that the capacitive area includes the sidewalls of the storage electrode and the cavity in the storage electrode. The capacitor is completed by forming a dielectric layer (54) over the storage electrode (50) and forming a conductive layer (56) over the dielectric layer (54) to act as a plate electrode capacitively-coupled to the storage electrode (50) through the dielectric layer (54). Other devices, systems and methods are also disclosed.

Abstract: An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is formed through the LOCOS structure (26). A channel stop implant region (40) is formed along the sidewalls of the trench (34). A trench plug (46) is used to fill the trench. The isolation structure thereby uses the isolation capabilities of trench isolation structures, but prevents the leakage currents common along trench sidewalls by isolating the trench sidewalls from the active region using the LOCOS structures.

Abstract: An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is formed through the LOCOS structure (26). A channel stop implant region (40) is formed along the sidewalls of the trench (34). A trench plug (46) is used to fill the trench. The isolation structure thereby uses the isolation capabilities of trench isolation structures, but prevents the leakage currents common along trench sidewalls by isolating the trench sidewalls from the active region using the LOCOS structures.

Abstract: A method for forming a storage capacitor (12) including the step of forming a storage node contact window (38) and forming a cavity (48) in the storage electrode (50) such that the capacitive area includes the sidewalls of the storage electrode and the cavity in the storage electrode. The capacitor is completed by forming a dielectric layer (54) over the storage electrode (50) and forming a conductive layer (56) over the dielectric layer (54) to act as a plate electrode capacitively-coupled to the storage electrode (50) through the dielectric layer (54). Other devices, systems and methods are also disclosed.

Abstract: A method of forming an integrated-circuit device (10) which provides increased packing of unrelated conductors such as first gate (14) and second gate (16). Strap (20) electrically connects conductor contact area (28) to moat contact area (30) and yet also overlies and overlaps gate (16) above the overlap area (27) without any danger of shorting first gate (14) to second gate (16). According to the invention, the possibility of shorting strap (20) to second gate (16) and hence first gate (14) to second gate (16), is eliminated in the processing sequence wherein second insulating layer (24) is patterned to expose conductor contact area (28) at a prior step in the processing sequence. Subsequently, a third insulating layer (26) is formed to re-cover conductor contact area (28), yet the thickness of third insulating layer (26) is substantially less than the combination of the thickness of third insulating layer (26) and second insulating layer (24).

Abstract: A semiconductor device is formed in an active region of a substrate. The device has first and second polysilicon strips which are aligned. The first polysilicon strip is somewhat wider than the second. A contact is formed between the second polysilicon strip and a region in the active region. The contact is ensured of not shorting to the first polysilicon strip by the use of an extra sidewall spacer. One sidewall is already present but is etched down to expose the second polysilicon strip. The etching down of the one sidewall spacer may also expose a corner of the first polysilicon strip. The extra sidewall spacer covers the potentially exposed corner. The first polysilicon strip can also have a neck portion protruding toward the second polysilicon strip and aligned with the second polysilicon strip. This further improves the margin by which the contact will avoid the corner of the first polysilicon strip.

Abstract: An N channel transistor is formed in an active region of a substrate and a P channel transistor is formed in a second layer of polysilicon with a first layer of polysilicon forming the gate for both transistors. An interlayer oxide between the first and second polysilicon layers is used as a gate insulator for the P channel transistor. The first and second layers of polysilicon are formed before the source and drain of the N channel transistor are formed in the active region. The first and second layers of polysilicon are selectively etched to form a self-aligned strip of first and second polysilicon. The self-aligned strip is over a portion of the active region to expose portions of the active region on both sides of the self-aligned strip. The exposed portions of the active region are doped to form the source and drain of the N channel transistor with a channel therebetween.

Abstract: A semiconductor process is provided for the formation of a very low resistance contact. After a straight wall contact is formed conventionally above a silicon substrate, a blanket metal barrier layer is deposited. A plurality of planar polysilicon layers are deposited above the metal barrier layer. The polysilicon layers have varying doping levels and are etched away. A byproduct gas of the etch reaction is monitored and the transition between polysilicon layers can be accurately noted. In this way, a layer of doped polysilicon is left above the metal barrier in the contact region. Metal may then be patterned over the entire structure to provide a low resistance reliable contact.