Patents by Inventor Sug-Woo Jung
Sug-Woo Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937476Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.Type: GrantFiled: May 4, 2023Date of Patent: March 19, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jin Sung An, Sung Ho Kim, Yong Jae Kim, Yun Hwan Park, Yoon Jee Shin, Sug Woo Jung, Hyun Wook Choi
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Publication number: 20240088158Abstract: A display device includes: a substrate; a polycrystalline silicon film on the substrate; and a first buffer film between the substrate and the polycrystalline silicon film and having one surface contacting the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first root mean square (RMS) roughness range, and the first RMS roughness range is 1.5 nm or less.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Inventors: Ki Hyun KIM, Young Gil PARK, Jin Suk LEE, Jai Sun KYOUNG, Sug Woo JUNG
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Publication number: 20240057411Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.Type: ApplicationFiled: May 4, 2023Publication date: February 15, 2024Inventors: Jin Sung AN, Sung Ho KIM, Yong Jae KIM, Yun Hwan PARK, Yoon Jee SHIN, Sug Woo JUNG, Hyun Wook CHOI
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Patent number: 11817458Abstract: A display device includes: a substrate; a polycrystalline silicon film on the substrate; and a first buffer film between the substrate and the polycrystalline silicon film and having one surface contacting the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first root mean square (RMS) roughness range, and the first RMS roughness range is 1.5 nm or less.Type: GrantFiled: July 21, 2020Date of Patent: November 14, 2023Assignee: Samsung Display Co., Ltd.Inventors: Ki Hyun Kim, Young Gil Park, Jin Suk Lee, Jai Sun Kyoung, Sug Woo Jung
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Patent number: 11610957Abstract: A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers the first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 ? to about 400 ?. A gate insulation layer covers the active pattern. A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern.Type: GrantFiled: January 28, 2021Date of Patent: March 21, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Tetsuhiro Tanaka, Yeong-Gyu Kim, Tae Sik Kim, Hee Yeon Kim, Ki Seong Seo, Seung Hyun Lee, Kyeong Woo Jang, Sug Woo Jung
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Patent number: 11367768Abstract: A display device according to an embodiment of the present disclosure includes a display panel including a display region and a non-display region, and a sensor unit which is disposed on the display panel and includes a sensing region and a non-sensing region. The sensor unit includes a touch sensor unit which detects a touch input in the sensing region and a photo sensor unit which detects ambient illuminance.Type: GrantFiled: March 30, 2021Date of Patent: June 21, 2022Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Kwang Hyeok Kim, Sang Hyun Jun, Mi Young Kim, So Yeon Park, Yong Hwan Park, Sug Woo Jung
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Publication number: 20220109038Abstract: A display device according to an embodiment of the present disclosure includes a display panel including a display region and a non-display region, and a sensor unit which is disposed on the display panel and includes a sensing region and a non-sensing region. The sensor unit includes a touch sensor unit which detects a touch input in the sensing region and a photo sensor unit which detects ambient illuminance.Type: ApplicationFiled: March 30, 2021Publication date: April 7, 2022Inventors: Kwang Hyeok KIM, Sang Hyun JUN, Mi Young KIM, So Yeon PARK, Yong Hwan PARK, Sug Woo JUNG
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Publication number: 20210257426Abstract: A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers lire first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 ? to about 400 ?. A gate insulation layer covers the active pattern A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern.Type: ApplicationFiled: January 28, 2021Publication date: August 19, 2021Inventors: Tetsuhiro TANAKA, Yeong-Gyu KIM, Tae Sik KIM, Hee Yeon KIM, Ki Seong SEO, Seung Hyun LEE, Kyeong Woo JANG, Sug Woo JUNG
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Publication number: 20210175258Abstract: A display device includes: a substrate; a polycrystalline silicon film on the substrate; and a first buffer film between the substrate and the polycrystalline silicon film and having one surface contacting the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first root mean square (RMS) roughness range, and the first RMS roughness range is 1.5 nm or less.Type: ApplicationFiled: July 21, 2020Publication date: June 10, 2021Inventors: Ki Hyun KIM, Young Gil PARK, Jin Suk LEE, Jai Sun KYOUNG, Sug Woo JUNG
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Patent number: 10305037Abstract: A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer.Type: GrantFiled: August 22, 2018Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Sug-woo Jung
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Patent number: 10249816Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.Type: GrantFiled: June 4, 2018Date of Patent: April 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Uk Kim, Jung-Moo Lee, Soon-Oh Park, Jung-Hwan Park, Sug-Woo Jung
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Publication number: 20180358557Abstract: A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer.Type: ApplicationFiled: August 22, 2018Publication date: December 13, 2018Inventor: Sug-woo JUNG
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Publication number: 20180277750Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.Type: ApplicationFiled: June 4, 2018Publication date: September 27, 2018Inventors: Jong-Uk KIM, Jung-Moo LEE, Soon-Oh PARK, Jung-Hwan PARK, Sug-Woo JUNG
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Patent number: 10062843Abstract: A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer.Type: GrantFiled: November 1, 2016Date of Patent: August 28, 2018Assignee: Samsung Electronics Co., Ltd.Inventor: Sug-woo Jung
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Patent number: 10026890Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.Type: GrantFiled: June 9, 2016Date of Patent: July 17, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Uk Kim, Jung-Moo Lee, Soon-Oh Park, Jung-Hwan Park, Sug-Woo Jung
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Publication number: 20170170237Abstract: A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer.Type: ApplicationFiled: November 1, 2016Publication date: June 15, 2017Inventor: Sug-woo JUNG
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Publication number: 20170092847Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.Type: ApplicationFiled: June 9, 2016Publication date: March 30, 2017Inventors: Jong-Uk KIM, Jung-Moo LEE, Soon-Oh PARK, Jung-Hwan PARK, Sug-Woo JUNG
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Patent number: 8841643Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.Type: GrantFiled: September 23, 2011Date of Patent: September 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Shin-Jae Kang, Sug-Woo Jung, Dong-Hyun Im, Chan-Mi Lee
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Patent number: 8237149Abstract: Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).Type: GrantFiled: April 14, 2011Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Gyu-Hwan Oh, Sug-Woo Jung, Dong-Hyun Im
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Publication number: 20120149166Abstract: A method of manufacturing a nonvolatile memory device includes forming an insulating film pattern, which includes apertures, on a substrate, forming a switching element in each of the apertures, forming a bottom electrode on the switching element by using a silicon (Si)-doped titanium nitride (TiN) film, and forming a variable resistance material pattern on the bottom electrode. The Si-doped TiN film is formed by repeatedly forming a TiN film and doping the TiN film with Si.Type: ApplicationFiled: November 21, 2011Publication date: June 14, 2012Inventors: Young-Lim PARK, Jin-Il Lee, Kyung-Min Chung, Sug-Woo Jung, Chang-Su Kim